9780470016428 - Latchup de Voldman (19 resultados)

HRD. Condición: New. New Book. Shipped from UK. Established seller since 2000.

Condición: new.

Condición: New. In.

Condición: As New. Unread book in perfect condition.

Condición: New.

Condición: New.

Condición: New.

Condición: As New. Unread book in perfect condition.

Condición: New. pp. xxii + 450 Illus.

Condición: New. This book addresses what is needed in future applications in order to avoid latchup in advanced technologies. A significant amount of new latchup issues and materials from the last twenty years are presented, such as the development of external and transient latchup concepts, and new tools such as the PICA tool. Num Pages: 474 pages, Illustrations. BIC Classification: TJFD5. Category: (P) Professional & Vocational. Dimension: 245 x 176 x 32. Weight in Grams: 932. . 2008. 1st Edition. Hardcover. . . . .

Condición: New. pp. xxii + 450.

Condición: New. Steven H. Voldman is an IEEE Fellow for Contributions in ESD Protection in CMOS, Silicon on Insulator and Silicon Germanium Technology . He has a B.S. engineering science from University of Buffalo (1979), a first M.S. EE (1981) from Massachusetts Institut.

Hardcover. Condición: Brand New. 1st edition. 472 pages. 10.00x7.00x1.00 inches. In Stock.

Condición: New. This book addresses what is needed in future applications in order to avoid latchup in advanced technologies. A significant amount of new latchup issues and materials from the last twenty years are presented, such as the development of external and transient latchup concepts, and new tools such as the PICA tool. Num Pages: 474 pages, Illustrations. BIC Classification: TJFD5. Category: (P) Professional & Vocational. Dimension: 245 x 176 x 32. Weight in Grams: 932. . 2008. 1st Edition. Hardcover. . . . . Books ship from the US and Ireland.

Buch. Condición: Neu. Neuware - Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration.Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand.This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as:\* latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers, and buried grids - from single- to triple-well CMOS;\* practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha (a) space, beta (b) space, new latchup design methods- connecting the theoretical to the practical analysis, and;\* examples of latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design, to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level.Latchup acts as a companion text to the author's series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology. Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration.

Condición: Sehr gut. Zustand: Sehr gut | Seiten: 472 | Sprache: Englisch | Produktart: Bücher | Written by a very well respected IBM Engineer with twenty years of latchup experience, Latchup in Semiconductor Technology provides a brief history to introduce the basics of latchup, and offers a comprehensive coverage of the subject, from the basic concepts and terminology, through to key ideas of latchup such as internal and external latchup, latchup sources, scaling, and instability.

Hardback. Condición: New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days.

Hardcover. Condición: new. Hardcover. Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand. This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as: latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers, and buried grids from single- to triple-well CMOS; practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha (a) space, beta (b) space, new latchup design methods connecting the theoretical to the practical analysis, and;examples of latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design, to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level. Latchup acts as a companion text to the authors series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology. Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration. This book addresses what is needed in future applications in order to avoid latchup in advanced technologies. A significant amount of new latchup issues and materials from the last twenty years are presented, such as the development of external and transient latchup concepts, and new tools such as the PICA tool. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability.

Hardcover. Condición: Brand New. 1st edition. 472 pages. 10.00x7.00x1.00 inches. In Stock. This item is printed on demand.