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Verification Methodology Manual for Low Power

David Flynn, Yoshio Inoue, Janick Bergeron, Srikanth Jadcherla

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ISBN 10: 160743413X / ISBN 13: 9781607434139
Editorial: Synopsys, 2009
Usado Condición: Good Encuadernación de tapa blanda
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Título: Verification Methodology Manual for Low ...

Editorial: Synopsys

Año de publicación: 2009

Encuadernación: Paperback

Condición del libro:Good

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Power management is now the biggest barrier to the continuation of Moore s law, and low power IC designs have introduced new classes of bugs and silicon failures. As a result, successful verification of low power designs has an immense impact on the overall success of a product. Today s verification tools have evolved to detect these bugs as early as at the RTL design stage, which reduces the risk of field failures. However, tools alone are not sufficient. A rigorous verification methodology for low power is the correct prescription for avoiding unpleasant and costly surprises.

Leveraging years of collective industry best practices, the Verification Methodology Manual for Low Power (VMM-LP) introduces a new verification methodology for low power and provides a blueprint for successful verification of low power designs. It describes the common causes of low power design failures, the impact of low power on the specification of power intent, the implementation of test plans, the setup of testbenches and the metrics of verification using assertions and coverage. The VMM-LP builds on the base classes in industry standard VMM to enable the deployment of a consistent, reusable, and scalable power-aware verification environment across multiple design projects within a company. In addition to benefitting from the extensive practical experience of the authors from ARM, Synopsys, and Renesas, the VMM-LP is also peer-reviewed by more than 30 low power design and verification experts from around the world.

About the Author:

Srikanth Jadcherla came to Synopsys as part of the ArchPro acquisition, where he was founder and CTO. Prior to ArchPro, Jadcherla was an IC designer and architect at companies such as WSI, Intel, Jasmine and Synopsys. He is a veteran of low power designs and pioneer of many energy efficiency techniques and principles. Jadcherla received an Intel Achievement Award for his work on low power and is the author of 12 patents. He is an honorary green evangelist/technical advisor to various companies ranging from solar energy suppliers to real estate developers. Recently, he has been advocating new paradigms in energy efficient design in semiconductor systems worldwide from both the supply and demand side of energy consumption.

Mr. Jadcherla holds a Bachelor's Degree in Electrical Engineering from IITMadras in India, and a Master's Degree in Computational Science and Engineering from the University of California, SantaBarbara.

Janick Bergeron is a Fellow at Synopsys Inc. responsible for the development and specification of the functional verification methodology to be supported by their digital simulation products. He is the author of the best-selling Verification Methodology Manual for SystemVerilog and of the Writing Testbenches book series. Both are the first industry references on modern functional verification techniques and methodologies.

Mr. Bergeron holds a Bachelors Degree in Engineering from the Universite du Quebec a Chicoutimi, a Master of Applied Sciences in Electrical Engineering from the University of Waterloo VLSI program, and an MBA from the University of Oregon through the Oregon Executive MBA program.

Yoshio Inoue is Chief Engineer of Design Technology Div. at Renesas Technology Corp., which was formed through the merger of semiconductor operations of Hitachi and Mitsubishi on April 1st, 2003.

He holds a Bachelor of Science Degree at Tokyo Denki University. He joined Mitsubishi Electric as a gate array design engineer in 1984. Since 1989 he has been involved in advanced EDA design methodology development and EDA design systems to support the US's high-speed, high-complexity SoC designs.

When Renesas was formed, he focused more on RTL prototyping technology for Japanese and US customers designs. He has expanded his area of focus to ultra low power design methodology such as application processors for cellular phones and is a pioneer in the area of hierarchical power management.

David Flynn, a Fellow in R&D at ARM Ltd., has been with the company since 1991, specializing in System-on-Chip IP deployment and methodology. He is the original architect behind ARM s synthesizable CPU family and the AMBA on-chip interconnect standard. His current research focus is low-power system-level design. He holds a number of patents in on-chip buses, low -power and embedded processing sub-system design and holds a Bachelr of Science Degree in Computer Science from Hatfield Polytechnic, UK and a Doctorate in Electronic Engineering from Loughborough University, UK. He is currently Visiting Professor with the Electronics and Computer Science Department at Southampton University, UK.

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