Hardcover. Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted on the fly by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engineers interested in adaptive techniques for low-power CMOS circuits. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.

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Detalles bibliogr�ficos

T�tulo: Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits (Hardcover)
Editor: Springer, Dordrecht
Fecha de publicaci�n: 2013
Idioma: Ingl�s
ISBN 10: 9400761953
ISBN 13: 9789400761957
Encuadernaci�n: Hardcover
Estado: new

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Sinopsis

Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted "on the fly" by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engineers interested in adaptive techniques for low-power CMOS circuits.

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Martin Wirnshofer received the Dipl.-Ing. degree in Electrical Engineering in 2007 from the Technische Universit�t M�nchen (TUM), Germany. His research on voltage reference circuits earned him the Outstanding Thesis Award by the German Association of Electrical Engineers (VDE). From 2007 to 2008 he was an analog designer with the Embedded Flash Memory Group at Infineon Technologies AG, Munich. Since 2008 he is a doctoral researcher at the Institute for Technical Electronics at TUM and has recently finished his Ph.D. project. He received the Excellence in Teaching Award by the Faculty of Electrical Engineering in 2010 and has authored and co-authored numerous international conference and journal publications. His research interests include low-power and low-voltage circuit design, adaptive circuit techniques and design methodologies for the nanoscale CMOS era. He is a member of the IEEE and the German Association of Electrical Engineers.

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