Ex-Corporate Library copy; with typical markings. Library label on front board and on spine tail. Very light surface rubbing on portions of boards. Else binding clean. Pages clean, but for library markings. ; TEH22A; 278 pages; Ex-Library.

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Detalles bibliogr�ficos

T�tulo

VLSI Placement and Global Routing Using Simulated Annealing

Editor

Kluwer Academic Publishers

Fecha de publicaci�n

1988

Idioma

Ingl�s

ISBN 10

0898382815

ISBN 13

9780898382815

Encuadernaci�n

Hardcover

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Sinopsis

From my B.E.E degree at the University of Minnesota and right through my S.M. degree at M.I.T., I had specialized in solid state devices and microelectronics. I made the decision to switch to computer-aided design (CAD) in 1981, only a year or so prior to the introduction of the simulated annealing algorithm by Scott Kirkpatrick, Dan Gelatt, and Mario Vecchi of the IBM Thomas 1. Watson Research Center. Because Prof. Alberto Sangiovanni-Vincentelli, my UC Berkeley advisor, had been a consultant at IBM, I re� ceived a copy of the original IBM internal report on simulated annealing approximately the day of its release. Given my background in statistical mechanics and solid state physics, I was immediately impressed by this new combinatorial optimization technique. As Prof. Sangiovanni-Vincentelli had suggested I work in the areas of placement and routing, it was in these realms that I sought to explore this new algorithm. My flJ'St implementation of simulated annealing was for an island-style gate array placement problem. This work is presented in the Appendix of this book. I was quite struck by the effect of a nonzero temperature on what otherwise appears to be a random in� terchange algorithm.

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