VLSI DESIGN VERIFICATION: Functional Verification, Simulation, Assertions, Coverage, Debugging, and Verification Methodologies (VLSI Design & Semiconductor Engineering)

Verification has quietly become the largest single engineering activity in modern semiconductor design, yet it is frequently taught, if it is taught at all, as a secondary topic appended to a design-focused digital systems curriculum, or learned haphazardly on the job through a patchwork of vendor documentation, internal training slides, and hard-won personal experience. This book grew out of a conviction that verification deserves to be taught as a coherent engineering discipline in its own right, with its own foundational principles, its own body of technique, and its own standards of rigor — not merely as a collection of tool-specific tips for using a particular simulator or a particular class library.
The organization of this book reflects that conviction. Rather than beginning with SystemVerilog syntax or UVM class hierarchies, the book opens by asking why verification is hard and why it matters economically, grounding the technical material that follows in the risk-management framing that experienced verification engineers eventually internalize, usually only after years of practice. From there, the book proceeds deliberately from foundations (digital design review, verification planning) through language and simulation fundamentals, into the advanced techniques that define contemporary practice — assertions, coverage, constrained-random methodology, UVM, and formal verification — before extending into the specialized domains a working verification engineer increasingly encounters on real industrial projects: emulation and prototyping, low-power verification, mixed-signal verification, and gate-level timing-aware verification. The book closes with the practical disciplines of debugging, regression management, and sign-off that determine how effectively all of the preceding technical material is actually applied under real schedule and resource constraints, and with a forward-looking discussion of how machine learning and Portable Stimulus are beginning to reshape the field.
This book is written for two overlapping audiences. For graduate students and advanced undergraduates encountering verification for the first time in a formal academic setting, it aims to provide the conceptual foundation and technical depth appropriate to a rigorous, semester-length course, complete with review questions designed to reinforce and test understanding of each chapter's material. For practicing engineers — whether newly joining a verification team or an experienced design engineer seeking a more systematic understanding of the verification discipline surrounding their work — it aims to provide both a coherent narrative explaining *why* the field's standard practices exist in their current form, and a practical reference detailing *how* those practices are actually applied.
Throughout the text, I have made a deliberate effort to explain not only what techniques exist but why they emerged, what specific limitation of a prior technique motivated their development, and what limitations they themselves retain — because a verification engineer who understands a technique's boundaries is far better equipped to recognize when that technique is, or is not, the right tool for a given verification challenge than one who has memorized only its mechanics. Historical case studies, including well-documented industry incidents such as the Intel Pentium FDIV bug and the Meltdown/Spectre disclosures, are included specifically to ground abstract discussion of verification risk in concrete, consequential reality.