VHDL for Simulation, Synthesis and Formal Proofs of Hardware (Paperback)

Descripción:

Paperback. The success of VHDL since it has been balloted in 1987 as an IEEE standard may look incomprehensible to the large population of hardware designers, who had never heared of Hardware Description Languages before (for at least 90% of them), as well as to the few hundreds of specialists who had been working on these languages for a long time (25 years for some of them). Until 1988, only a very small subset of designers, in a few large companies, were used to describe their designs using a proprietary HDL, or sometimes a HDL inherited from a University when some software environment happened to be developped around it, allowing usability by third parties. A number of benefits were definitely recognized to this practice, such as functional verification of a specification through simulation, first performance evaluation of a tentative design, and sometimes automatic microprogram generation or even automatic high level synthesis. As there was apparently no market for HDL's, the ECAD vendors did not care about them, start-up companies were seldom able to survive in this area, and large users of proprietary tools were spending more and more people and money just to maintain their internal system. The success of VHDL since it has been balloted in 1987 as an IEEE standard may look incomprehensible to the large population of hardware designers, who had never heared of Hardware Description Languages before (for at least 90% of them), as well as to the few hundreds of specialists who had been working on these languages for a long time (25 years for some of them). Until 1988, only a very small subset of designers, in a few large companies, were used to describe their designs using a proprietary HDL, or sometimes a HDL inherited from a University when some software environment happened to be developped around it, allowing usability by third parties. A number of benefits were definitely recognized to this practice, such as functional verification of a specification through simulation, first performance evaluation of a tentative design, and sometimes automatic microprogram generation or even automatic high level synthesis. As there was apparently no market for HDL's, the ECAD vendors did not care about them, start-up companies were seldom able to survive in this area, and large users of proprietary tools were spending more and more people and money just to maintain their internal system. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability. N° de ref. del artículo 9781461365822

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Sinopsis:

Reseña del editor: The emergence of Vhdl as a standard for hardware description languages helped disseminate the use of such languages among Ic designers. The creation of the standard however does not mean that all work has ceased. Research continues in the use of the language and on improvements of the standard.
This book presents the latest research on four key issues related to the use of Vhdl. The first part covers simulation of circuits using Vhdl, in which timing and switching are central themes. Part Ii looks at the combination of synthesis and Vhdl in designing circuits. This includes a case study of chip design using silicon 1076. Advances in the formal verification of Vhdl designs are given in Part Iii. This relatively new area in the use of Vhdl is developing rapidly into an important issue for speeding the design of circuits. The final part considers modelling issues and system level design.
The contributors are based on specially selected papers from the Euro-Vhdl conferences in 1990 and 1991. These papers have been updated and expanded to give the reader the very latest state-of-the-art in the use of Vhdl for circuit design.