Universal Verification Methodology Based Verification Environment: Theory and Practice
Jain, Abhishek
ISBN 10: 3659476048 ISBN 13: 9783659476044
Editorial: LAP LAMBERT Academic Publishing, 2014
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Ever increasing silicon design complexity and transistor density, product differentiation and time to market are major factors creating huge pressure on complete design flow. This book covers Verification phase by describing the concepts of Universal Verification Methodology (UVM) and by presenting a pragmatic approach of developing efficient and unified advanced verification environment at all levels using Universal Verification Methodology along with Assertion based verification, hardware acceleration and Transaction Level Modeling. This book is written primarily for verification engineers performing verification of complex IP blocks or entire system-on-chip (SoC) designs. However, much of material will also be of interest to SoC project managers as well as designers to learn more about verification. Furthermore, this book includes detailed information about verification environment for one case which can be easily used as reference for other cases.
Acerca del autor: Abhishek Jain, Technical Manager at STMicroelectronics, India, has done M.Tech in Computer Science from IETE, M.Sc. Electronics from University of Delhi and PGDBA in Operations Management from Symbiosis. Driving key activities on Functional Verification Flow in Imaging group of STMicroelectronics.Doing Research in Efficient Verification Management.
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Título: Universal Verification Methodology Based ...
Editorial: LAP LAMBERT Academic Publishing
Año de publicación: 2014
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Universal Verification Methodology Based Verification Environment : Theory and Practice
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Universal Verification Methodology Based Verification Environment
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Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Jain AbhishekAbhishek Jain, Technical Manager at STMicroelectronics, India, has done M.Tech in Computer Science from IETE, M.Sc. Electronics from University of Delhi and PGDBA in Operations Management from Symbiosis. Driving key acti. Nº de ref. del artículo: 5158377
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Universal Verification Methodology Based Verification Environment: Theory and Practice
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Ever increasing silicon design complexity and transistor density, product differentiation and time to market are major factors creating huge pressure on complete design flow. This book covers Verification phase by describing the concepts of Universal Verification Methodology (UVM) and by presenting a pragmatic approach of developing efficient and unified advanced verification environment at all levels using Universal Verification Methodology along with Assertion based verification, hardware acceleration and Transaction Level Modeling. This book is written primarily for verification engineers performing verification of complex IP blocks or entire system-on-chip (SoC) designs. However, much of material will also be of interest to SoC project managers as well as designers to learn more about verification. Furthermore, this book includes detailed information about verification environment for one case which can be easily used as reference for other cases. 140 pp. Englisch. Nº de ref. del artículo: 9783659476044
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Universal Verification Methodology Based Verification Environment
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ISBN 10: 3659476048
ISBN 13: 9783659476044
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Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Ever increasing silicon design complexity and transistor density, product differentiation and time to market are major factors creating huge pressure on complete design flow. This book covers Verification phase by describing the concepts of Universal Verification Methodology (UVM) and by presenting a pragmatic approach of developing efficient and unified advanced verification environment at all levels using Universal Verification Methodology along with Assertion based verification, hardware acceleration and Transaction Level Modeling. This book is written primarily for verification engineers performing verification of complex IP blocks or entire system-on-chip (SoC) designs. However, much of material will also be of interest to SoC project managers as well as designers to learn more about verification. Furthermore, this book includes detailed information about verification environment for one case which can be easily used as reference for other cases.Books on Demand GmbH, Überseering 33, 22297 Hamburg 140 pp. Englisch. Nº de ref. del artículo: 9783659476044
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Universal Verification Methodology Based Verification Environment : Theory and Practice
Publicado por
LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659476048
ISBN 13: 9783659476044
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Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Ever increasing silicon design complexity and transistor density, product differentiation and time to market are major factors creating huge pressure on complete design flow. This book covers Verification phase by describing the concepts of Universal Verification Methodology (UVM) and by presenting a pragmatic approach of developing efficient and unified advanced verification environment at all levels using Universal Verification Methodology along with Assertion based verification, hardware acceleration and Transaction Level Modeling. This book is written primarily for verification engineers performing verification of complex IP blocks or entire system-on-chip (SoC) designs. However, much of material will also be of interest to SoC project managers as well as designers to learn more about verification. Furthermore, this book includes detailed information about verification environment for one case which can be easily used as reference for other cases. Nº de ref. del artículo: 9783659476044
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Universal Verification Methodology Based Verification Environment Theory and Practice
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LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659476048
ISBN 13: 9783659476044
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