Reuse Methodology Manual for System-on-a-Chip Designs

Michael Keating

ISBN 10: 0792385586 ISBN 13: 9780792385585

Editorial: Kluwer Academic Publishers, 1999

Idioma: Ingl�s

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Detalles bibliogr�ficos

T�tulo

Reuse Methodology Manual for System-on-a-Chip Designs

Editor

Kluwer Academic Publishers

Fecha de publicaci�n

1999

Idioma

Ingl�s

ISBN 10

0792385586

ISBN 13

9780792385585

Encuadernaci�n

Hardback

Edici�n

2� Edici�n

Estado

New

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Sinopsis

Foreword. Preface to the Second Edition. Acknowledgements. 1. Introduction. 2. The System-on-a-Chip Design Process. 3. System-Level Design Issues: Rules and Tools. 4. The Macro Design Process. 5. RTL Coding Guidelines. 6. Macro Synthesis Guidelines. 7. Macro Verification Guidelines. 8. Developing Hard Macros. 9. Macro Deployment: Packaging for Reuse. 10. System Integration with Reusable Macros. 11. System-Level Verification Issues. 12. Data and Project Management. 13. Implementing a Reuse Process. Bibliography.

Rese�a del editor

Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the vast numbers of gates now available. This work outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. It is an attempt to capture and improve on current practices in the industry, and to give a coherent, integrated view of the design process.

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