The RISC-V Reader: An Open Architecture Atlas

The RISC-V Reader is a concise introduction and reference for embedded systems programmers, students, and the curious to a modern, popular, open architecture. RISC-V spans from the cheapest 32-bit embedded microcontroller to the fastest 64-bit cloud computer. The text shows how RISC-V followed the good ideas of past architectures while avoiding their mistake.

Highlights include:

• Introduces the RISC-V instruction set in only 100 pages, including 75 figures
• An Instruction Translator Guide to help translate assembly language programs from ARM-32 and x86-32 instruction sets to RISC-V
• 2-page RISC-V Reference Card that summarizes all instructions
• 50-page Instruction Glossary that defines every instruction in detail
• 75 spotlights of good architecture design using margin icons
• 50 sidebars with interesting commentary and RISC-V history
• 25 quotes to pass along wisdom of noted scientists and engineers

Ten chapters introduce each component of the modular RISC-V instruction set--often contrasting code compiled from C to RISC-V versus the older ARM, Intel, and MIPS architectures--but readers can start programming after Chapter 2.

Praise for The RISC-V Reader:

• “This timely book concisely describes the simple, free and open RISC-V ISA that is experiencing rapid uptake in many different computing sectors.” Krste Asanovic, University of California, Berkeley, one of the four architects of RISC-V
• “I like RISC-V and this book as they are elegant—brief, to the point, and complete.” C. Gordon Bell, a computer architecture pioneer
• “ This handy little book effortlessly summarizes all the essential elements of the RISC-V Instruction Set Architecture, a perfect reference guide for students and practitioners alike.” Professor Randy Katz, University of California, Berkeley, one of the inventors of RAID storage systems
• “This clearly-written book offers a good introduction to RISC-V, augmented with insightful comments on its evolutionary history and comparisons with other familiar architectures.” John Mashey, one of the designers of the MIPS architecture
• “This book tells what RISC-V can do and why its designers chose to endow it with those abilities.” Ivan Sutherland, the father of computer graphics
• “RISC-V will change the world, and this book will help you become part of that change.” Professor Michael B. Taylor, University of Washington
• “This book will be an invaluable reference for anyone working with the RISC-V ISA.” Megan Wachs, PhD, SiFive Engineer

David Patterson retired after 40 years as a Professor of Computer Science at UC Berkeley in 2016, and then joined Google Brain as a distinguished engineer. He also serves as Vice-Chair of the Board of Directors of the RISC-V Foundation. In the past, he was named Chair of Berkeley’s Computer Science Division and was elected to be Chair of the CRA and President of the Association for Computing Machinery. In the 1980s, he led four generations of Reduced Instruction Set Computer (RISC) projects, which inspired Berkeley’s latest RISC to be named “RISC Five.” Along with Andrew Waterman, he was one of the four architects of RISC-V. Beyond RISC, his best-known research projects are Redundant Arrays of Inexpensive Disks (RAID) and Networks of Workstations (NOW). This research led to many papers, 7 books, and more than 35 honors, including election to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame as well as being named a Fellow of the Computer History Museum, ACM, IEEE, and both AAAS organizations. His teaching awards include the Distinguished Teaching Award (UC Berkeley), the Karlstrom Outstanding Educator Award (ACM), the Mulligan Education Medal (IEEE), and the Undergraduate Teaching Award (IEEE). He also won Textbook Excellence Awards (“Texty”) from the Text and Academic Authors Association for a computer architecture book and for a software engineering book. He received all his degrees from UCLA, which awarded him an Outstanding Engineering Academic Alumni Award.

Andrew Waterman serves as SiFive’s Chief Engineer and co-founder. SiFive was founded by the creators of the RISC-V architecture to provide low-cost custom chips based on RISC- V. He received his PhD in Computer Science from UC Berkeley, where, weary of the vagaries of existing instruction set architectures, he co-designed the RISC-V ISA and the first RISC-V microprocessors. Andrew is one of the main contributors to the open-source RISC-V-based Rocket chip generator, the Chisel hardware construction language, and the RISC-V ports of the Linux operating system kernel and the GNU C Compiler and C Library. He also has an MS from UC Berkeley, which was the basis of the RVC extension for RISC-V, and a BSE from Duke University.