Paperback. Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems.This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence. Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.

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Detalles bibliogr�ficos

T�tulo: A Primer on Memory Consistency and Cache Coherence, Second Edition (Paperback)
Editor: Springer International Publishing AG, Cham
Fecha de publicaci�n: 2020
Idioma: Ingl�s
ISBN 10: 3031006364
ISBN 13: 9783031006364
Encuadernaci�n: Paperback
Edici�n: 2� Edici�n
Estado: new

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Sinopsis

Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems.

This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.

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Vijay Nagarajan is a Reader at the School of Informatics at the University of Edinburgh. He received a Ph.D. in Computer Science from University of California, Riverside. His research interests span computer architecture, compilers, and computer systems with a focus on memory consistency models and cache coherence protocols. He is a recipient of the Intel early career faculty honour award, a PACT best paper award, and an IEEE Top Picks honorable mention. He has served (or is currently serving) on multiple program committees including ISCA, MICRO, and HPCA. He was General Chair of LCTES 2017 and is currently serving as an Associate Editor of IEEE Computer Architecture Letters (IEEE CAL).Daniel J. Sorin is Professor of Electrical and Computer Engineering and of Computer Science at Duke University. His research interests are in computer architecture, including dependable architectures, verification-aware processor design, and memory system design. He received a Ph.D. and M.S. in electrical and computer engineering from the University of Wisconsin, and he received a BSE in electrical engineering from Duke University. He is the recipient of an NSF Career Award, and he was a Distinguished Visiting Fellow of the Royal Academy of Engineering (UK). He is the Editor-in-Chief of IEEE Computer Architecture Letters, and he is a Founder and Chief Architect of Realtime Robotics, Inc. He is the author of a previous Synthesis Lecture, Fault Tolerant Computer Architecture (2009).Mark D. Hill is John P. Morgridge Professor and Gene M. Amdahl Professor of Computer Sciences at the University of Wisconsin-Madison, where he also has a courtesy appointment in Electrical and Computer Engineering. His research interests and accomplishments are in parallel-computer system design (e.g., data-race-free memory consistency), memory system design (3C model: compulsory, capacity, and conflict misses), and computer simulation (GEMS and gem5). Hill's work is highly collaborative withover 160 co-authors and especially his long-time colleague David A. Wood. He received the 2019 Eckert-Mauchly Award and 2009 ACM SIGARCH Alan Berenbaum Distinguished Service Award. Hill is a fellow of IEEE and the ACM. He served as Chair of the Computer Community Consortium from 2018-2020 and as Wisconsin Computer Sciences Department Chair from 2014-2017. Hill has a Ph.D. in Computer Science from the University of California, Berkeley.David A. Wood is Professor Emeritus of Computer Sciences at the University of Wisconsin, Madison, where he was the Sheldon B. Lubar Chair in Computer Sciences, the Amarand Balinder Sohi Professor in Computer Science, and held a courtesy appointment in Electrical and Computer Engineering. Dr. Wood has a Ph.D. in Computer Science (1990) from UC Berkeley. Dr. Wood is an ACM Fellow (2006), IEEE Fellow (2004), UW Vilas Associate (2011), UW Romnes Fellow (1999), and NSF PYI (1991). Dr. Wood served as Chair of ACM SIGARCH, Area Editor (Computer Systems) of ACM TOMACS, Associate Editor of ACM TACO, Program Committee Chairman of ASPLOS-X (2002), and served on numerous program committees. Dr. Wood has published over 100 technical papers and is an inventor on 19 U.S. patents. Dr. Wood co-led the Wisconsin Wind Tunnel and Wisconsin Multifacet projects with his long-time collaborator Mark D. Hill.

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