Low-Voltage CMOS Log Companding Analog Design

Idioma: inglés

Editorial: Springer US Jun 2003, 2003

140207445X / 9781402074455

Serie: Libro 20 de 260 - The Springer International Series in Engineering and Computer Science

Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, AlemaniaBuchWeltWeit Ludwig Meier e.K.

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This item is printed on demand - it takes 3-4 days longer - Neuware -Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering. 220 pp. Englisch.…

N° de ref. del artículo 9781402074455

Título
Low-Voltage CMOS Log Companding Analog Design
Autor
Francisco Serra-Graells
Editorial
Springer US Jun 2003
Año de publicación
2003
Estado
Neu
Encuadernación
Buch
Idioma
inglés
ISBN 10
140207445X
ISBN 13
9781402074455
Peso del artículo
500 gramos
Dimensiones
241x160x17 mm
Serie
Libro 20 de 260: The Springer International Series in Engineering and Computer Science

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Alemania

Vendedor de 5 estrellas

Vendedor de IberLibro desde 11 de enero de 2012

Tarifas de envío de Alemania a Estados Unidos de America

ArtículoDe 5 a 15 días hábilesDe 5 a 15 días hábiles
Primer artículoEUR 23,00EUR 23,00
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BuchWeltWeit Ludwig Meier e.K.

Alemania