Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

Rese�a del editor

"Sobre este t�tulo" puede pertenecer a otra edici�n de este libro.

Descripci�n de la librer�a

Professional Book Seller offering fast shipping and hassle-free returns for every order. Our 100% satisfaction policy guarantees that you get the best product and the best service at the best price!

Ver la p�gina web de la librer�a

Informaci�n empresarial del vendedor

Basi6 International LLC
1018 Camino Lago, Irving, TX, 75039, U.S.A.

Condiciones de venta y env�o

Condiciones de venta

Professional Book Seller shipping from Multiple Locations Worldwide for fastest delivery possible!

Condiciones de env�o

All orders shipped via FedEx or DHL and delivered to your doorstep within 3-5 days. We do not ship to P.O.Boxes and a proper street address must be provided to avoid any delays.

Informaci�n detallada sobre el vendedor