Neuware -An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips.Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / ReferencesSpringer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 112 pp. Englisch.

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T�tulo: An Introduction to Logic Circuit Testing
Editor: Springer International Publishing, Springer International Publishing Okt 2008
Fecha de publicaci�n: 2008
Idioma: Ingl�s
ISBN 10: 3031797841
ISBN 13: 9783031797842
Encuadernaci�n: Taschenbuch
Estado: Neu

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Sinopsis

An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References

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Parag K. Lala is the Cary and Lois Patterson Chair and Founding Chairman of Electrical Engineering at Texas A&M University, Texarkana; he was also the interim Chair of the Computer and Information Science Department at A&M, Texarkana for a year. Before his current position, he was the Thomas Mullins Chair Professor of Computer Engineering at the University of Arkansas at Fayetteville. He received his M.Sc.(Eng.) degree from the Kings College, University of London, and his Ph.D. from The City University of London. His current research interests are in online testable logic, biologically inspired digital system design, fault-tolerant computing, and hardware-based molecular sequence matching. He has supervised more than 30 M.Sc. and Ph.D. theses and authored or coauthored over 135 papers. He is the author of six books: Fault-Tolerant and Fault-Testable Hardware Design (Prentice-Hall, 1985), Digital System Design Using PLDs (Prentice-Hall, 1990), Practical Digital Logic Design and Testing (Prentice-Hall, 1996), Digital Circuit Testing and Testability (Academic Press, 1997), and Self-Checking, Fault-Tolerant Digital Design (Morgan-Kaufmann, 2001), and Principles of Modern Digital Design (John Wiley and Sons, 2007). He was selected Outstanding Educator in 1994 by the Central North Carolina section of the IEEE. In 1998 he was awarded a D.Sc.(Eng.) degree in electrical engineering by the University of London for contributions to digital hardware design and testing. He was made a Fellow of the IEEE in 2001 for contribution to the development of self-checking logic and associated checker design. He is also a fellow of the IET (Institute of Science and Technology) in the United Kingdom.

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