T�tulo: Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow
Editor: VDM Verlag, DE
Fecha de publicaci�n: 2008
Idioma: Ingl�s
ISBN 10: 3639106903
ISBN 13: 9783639106909
Encuadernaci�n: Paperback
Estado: New
Dimensiones: 15,01 cent�metros de ancho por 0,53 de alto por 22 de largo
Peso: 141 gramos

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Sinopsis

Modern electronic design automation tools can be used to apply a variety of transformations to hardware blocks in an effort to achieve performance and power savings. A number of such transformations require tools with intimate knowledge of the design's timing characteristics. Static timing analysis estimates the worst-case timing behavior of hardware data flow graphs. The static timing analyzer described in this book operates on data flow graphs which are generated as intermediate representations within a C to VHDL hardware acceleration compiler. Two additional tools were then developed which utilize the results of the static timing analysis. An automated pipelining tool was developed to increase the throughput of large blocks of combinational logic generated by the compiler. Another tool was designed to mitigate power consumption resulting from combinational glitching. By inserting special signal buffers with preselected propagation delays, known as delay elements, functional units can be kept inactive until their inputs stabilize. This book explores these tools as well as the various design tradeoffs resulting from their use.

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