High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection presents state-of-the art high-level synthesis methodologies for hardware security and trust, including IP protection through synthesis-based watermarking and structural obfuscation. All modern electronic gadgets have complex system-on-chips (SoCs) that rely heavily on data intensive application specific processors, for digital signal processing (DSP), machine learning, and image processing applications. These data-intensive cores, in the form of intellectual property (IP), form an integral part of various modern equipment and consumer applications, such as smart phones, smart watches, and tablets. High level synthesis (HLS) frameworks play a pivotal role in designing these application specific processors. However, the design of such processors can be exposed to several trust issues and hardware security threats, such as IP piracy, fraud IP ownership, and reverse engineering. Written by an expert author, this book is a source of information for readers on HLS solutions for hardware security. It covers topics such as HLS-based watermarking using retinal biometrics, HLS-based structural obfuscation, and detective countermeasure against HLS-based hardware Trojan attacks. This book is a useful resource for researchers, graduate students, and practising engineers working in electronics and chip design.

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T�tulo: High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection
Editor: Institution of Engineering and Technology, GB
Fecha de publicaci�n: 2024
Idioma: Ingl�s
ISBN 10: 1837241171
ISBN 13: 9781837241170
Encuadernaci�n: Hardback
Estado: New
Dimensiones: 15,6 cent�metros de ancho por 1,91 de alto por 23,39 de largo

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Sinopsis

High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection presents state-of-the art high-level synthesis methodologies for hardware security and trust, including IP protection through synthesis-based watermarking and structural obfuscation.

All modern electronic gadgets have complex system-on-chips (SoCs) that rely heavily on data intensive application specific processors, for digital signal processing (DSP), machine learning, and image processing applications. These data-intensive cores, in the form of intellectual property (IP), form an integral part of various modern equipment and consumer applications, such as smart phones, smart watches, and tablets.

High level synthesis (HLS) frameworks play a pivotal role in designing these application specific processors. However, the design of such processors can be exposed to several trust issues and hardware security threats, such as IP piracy, fraud IP ownership, and reverse engineering.

Written by an expert author, this book is a source of information for readers on HLS solutions for hardware security. It covers topics such as HLS-based watermarking using retinal biometrics, HLS-based structural obfuscation, and detective countermeasure against HLS-based hardware Trojan attacks.

This book is a useful resource for researchers, graduate students, and practising engineers working in electronics and chip design.

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Anirban Sengupta is a full professor in the Department of Computer Science and Engineering at the Indian Institute of Technology (IIT) Indore, India. He has more than 300 publications and patents, including 6 books, to his credit. He is the recipient of awards and honors such as fellow of IET, fellow of British Computer Society, fellow of IETE, IEEE Chester Sall Memorial Consumer Electronics Award, IEEE distinguished lecturer, IEEE distinguished visitor, IEEE CESoc Outstanding Editor Award, IEEE CESoc Best Research Award from CEM, Best Research paper Award in IEEE ICCE 2019, IEEE Computer Society TCVLSI Outstanding Editor Award, and IEEE TCVLSI Best Paper Award in IEEE iNIS 2017. He held or holds around 18 editorial positions in IEEE and IET journal boards. He is consistently ranked in Stanford University's Top 2% Scientists globally. Details available at: http://www.anirban-sengupta.com/index.php.

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