Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms: A Cross-layer Approach
Idioma: inglés
Editorial: Springer, 2018
- Tapa dura
- Nuevo
Librería: Ria Christie Collections, Uxbridge, Reino UnidoRia Christie Collections
Vendedor de IberLibro desde 25 de marzo de 2015
Condición: Nuevo
EUR 131,29
Cantidad disponible: Más de 20 disponibles
Añadir al carritoDescripción del artículo del vendedor
In English.
N° de ref. del artículo ria9783319919614_new
- Título
- Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms: A Cross-layer Approach
- Editorial
- Springer
- Año de publicación
- 2018
- Estado
- New
- Encuadernación
- Encuadernación de tapa dura
- Idioma
- inglés
- ISBN 10
- 331991961X
- ISBN 13
- 9783319919614
- Peso del artículo
- 767 gramos
This book describes the state-of-the art of industrial and academic research in the architectural design of heterogeneous, multi/many-core processors. The authors describe methods and tools to enable next-generation embedded and high-performance heterogeneous processors to confront cost-effectively the inevitable variations by providing Dependable-Performance: correct functionality and timing guarantees throughout the expected lifetime of a platform under thermal, power, and energy constraints. Various aspects of the reliability problem are discussed, at both the circuit and architecture level, the intelligent selection of knobs and monitors in multicore platforms, and systematic design methodologies. The authors demonstrate how new techniques have been applied in real case studies from different applications domain and report on results and conclusions of those experiments.
- Enables readers to develop performance-dependable heterogeneous multi/many-core architectures
- Describes system software designs that support high performance dependability requirements
- Discusses and analyzes low level methodologies to tradeoff conflicting metrics, i.e. power, performance, reliability and thermal management
- Includes new application design guidelines to improve performance dependability
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Acerca del autor
William Fornaciari is Associate Professor at Politecnico di Milano, Dipartimento di Elettronica e Informazione. He published six books and over 150 papers in international journals and conference proceedings, collecting five best paper awards, one certification of appreciation from IEEE and holds two international patents on low power design solutions. Since 1993 he is member of program and scientific committees and chair of international conferences in the field of computer architectures, EDA and system-level design. Since 1997 has been involved in 13 EU-funded international projects and he has been part of the pool of experts of the Call For Tender No.964-2005 – WING – Watching IST INnovation and knowledge, studying the impact of FP5 and FP6 expenditure for the EC, in the perspective to support the identification of FP7 and Horizon2020 research directions.
Recently, he participated to the MULTICUBE project for design space exploration and to the IP WASP on wireless sensor networks. In FP7 he has been workpackage leader for the IP COMPLEX project and Project Technical Manager of 2PARMA and also contributes to the Artemis SMECY project. Currently, still in FP7, he is project coordinator of the project HARPA on run-time management t
o achieve dependable performance and Workpackage leader of the CONTREX project on design of systems with mixed criticalities. He is also project reviewer for the European Commission and national research bodies in Europe. During the last 20 years he has worked as consultant for both management and technical issues for many ICT industries, gaining a relevant experience in technology transfer and product development. His current research interests include embedded systems design methodologies, real-time operating systems, energy-aware design of sw and hw, runtime management of resources, reconfigurable computing and wireless sensor networks, design and optimization of multi-core systems, NoC design and optimization, reliability.Dimitrios Soudris received his Diploma in Electrical Engineering from the University of Patras, Greece, in 1987. He received the Ph.D. Degree in Electrical Engineering, from the University of Patras in 1992. He was working as a Professor in Dept. of Electrical and Computer Engineering, Democritus University of Thrace for thirteen years since 1995. He is currently working as Associate Professor in School of Electrical and Computer Engineering, Dept. Computer Science of National Technical University of Athens, Greece. His research interests include embedded systems design, reconfigurable architectures, reliability and low power VLSI design. He has published more than 340 papers in international journals and conferences. Also, he is coauthor/coeditor in seven books of Kluwer and Springer. He is leader and principal investigator in numerous research projects funded from the Greek Government and Industry, European Commission (ESPRIT II-III-IV and 5th & 7th IST), ENIAC-JU and European Space Agency. He has served as General Chair and Program Chair for PATMOS 99 and 2000, respectively, General Chair of IFIP-VLSI-SOC 2008 and General Co-Chair of PARMA Workshop 2013. Also, he received an award from INTEL and IBM for the EU project LPGD 25256, awards in ASP-DAC 05 and VLSI 05 for EU AMDREL project IST-2001-34379.
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Ria Christie Collections
Uxbridge, Reino Unido
Vendedor de IberLibro desde 25 de marzo de 2015
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