Sinopsis
To date, the most common form of simulators of computer systems are software-based running on standard computers. One promising approach to improve simulation performance is to apply hardware, specifically reconfigurable hardware in the form of field programmable gate arrays (FPGAs). This manuscript describes various approaches of using FPGAs to accelerate software-implemented simulation of computer systems and selected simulators that incorporate those techniques. More precisely, we describe a simulation architecture taxonomy that incorporates a simulation architecture specifically designed for FPGA accelerated simulation, survey the state-of-the-art in FPGA-accelerated simulation, and describe in detail selected instances of the described techniques. Table of Contents: Preface / Acknowledgments / Introduction / Simulator Background / Accelerating Computer System Simulators with FPGAs / Simulation Virtualization / Categorizing FPGA-based Simulators / Conclusion / Bibliography / Authors' Biographies
Acerca del autor
Hari Angepat is a Ph.D. candidate at the University of Texas at Austin. He holds a B.Eng in Computer Engineering from McGill University and an M.S. in Computer Engineering from the University of Texas at Austin. Hari is interested in developing domain-specific FPGA microarchitectures and productivity tools to enable widespread adoption of hardware acceleration. Between 2008-2012, Hari led the FAST-MP project that enabled accurate functional-first simulation of multiprocessor systems on FPGAs.Derek Chiou is a Principal Architect at Microsoft where he leads a team working on FPGAs for data center applications. He is also an Associate Professor at e University of Texas at Austin where his research areas are FPGA acceleration, high performance computer simulation, rapid system design, computer architecture, parallel computing, Internet router architecture, and network processors. In a past life, Dr. Chiou was a system architect and led the performance modeling team at Avici Systems, a manufacturer of terabit core routers. Dr. Chiou received his Ph.D., S.M., and S.B. degrees in Electrical Engineering and Computer Science from MIT.Eric S. Chung is a Researcher at Microsoft Research in Redmond. Eric is interested prototyping and developing productive ways to harness massively parallel hardware systems that incorporate specialized hardware such as FPGAs. Eric received his Ph.D. in 2011 from Carnegie Mellon University and was the recipient of the Microsoft Research Fellowship award in 2009. His paper on CoRAM, a memory abstraction for programming FPGAs more effectively, received the best paper award in FPGA'11. Between 2005 and 2011, Eric led the ProtoFlex project that enabled practical FPGA-accelerated simulation of full-system multiprocessors.James C. Hoe is Professor of Electrical and Computer Engineering at Carnegie Mellon University. He received his Ph.D. in EECS from Massachusetts Institute of Technology in 2000 (S.M., 1994). He received his B.S. in EECS from UC Berkeley in 1992. He is a Fellow of IEEE. Dr. Hoe is interested in many aspects of computer architecture and digital hardware design, including the specific areas of FPGA architecture for computing; digital signal processing hardware; and high-level hardware design and synthesis. He was a contributor to RAMP (Research Accelerator for Multiple Processors). He worked on the ProtoFlex FPGA-accelerated simulation project between 2005 and 2011 with Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, Babak Falsafi, and Ken Mai. Earlier, he worked on the SMARTS sampling simulation project.
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