Energy-Aware System Design: Algorithms and Architectures

Power consumption becomes the most important design goal in a wide range of electronic systems. There are two driving forces towards this trend: continuing device scaling and ever increasing demand of higher computing power. First, device scaling continues to satisfy Moore’s law via a conventional way of scaling (More Moore) and a new way of exploiting the vertical integration (More than Moore). Second, mobile and IT convergence requires more computing power on the silicon chip than ever. Cell phones are now evolving towards mobile PC. PCs and data centers are becoming commodities in house and a must in industry. Both supply enabled by device scaling and demand triggered by the convergence trend realize more computation on chip (via multi-core, integration of diverse functionalities on mobile SoCs, etc.) and finally more power consumption incurring power-related issues and constraints.

Energy-Aware System Design: Algorithms and Architectures provides state-of-the-art ideas for low power design methods from circuit, architecture to software level and offers design case studies in three fast growing areas of mobile storage, biomedical and security.

Important topics and features:

- Describes very recent advanced issues and methods for energy-aware design at each design level from circuit and architecture to algorithm level, and also covering important blocks including low power main memory subsystem and on-chip network at architecture level

- Explains efficient power conversion and delivery which is becoming important as heterogeneous power sources are adopted for digital and non-digital parts

- Investigates 3D die stacking emphasizing temperature awareness for better perspective on energy efficiency

- Presents three practical energy-aware design case studies; novel storage device (e.g., solid state disk), biomedical electronics (e.g., cochlear and retina implants), and wireless surveillance camerasystems.

Researchers and engineers in the field of hardware and software design will find this book an excellent starting point to catch up with the state-of-the-art ideas of low power design.

Chong-Min Kyung has joined KAIST in 1983, and currently holds Hynix Chair Professorship at the Department of Electrical Engineering, KAIST. He has published more than 280 international Journal and Conference papers on CAD algorithms, 3-D graphics, System-on-a-Chip design and verification methodology, RISC/CISC microprocessors, VLIW and reconfigurable DSP cores, various video CODEC algorithms, and  energy-aware smart sensor design. His current research includes system-level low-power design, electrical/thermal co-design in 3D IC, architectures of H.264 video CODEC and rate-distortion-power optimization.

He is founding Director of the IDEC(Integrated Circuit Design Education Center) supporting over 60 universities in Korea for MPW chip fabrication since 1995. He served as General Chair in the Korean Semiconductor Conference 2002, ISOCC 2004, A-SSCC 2007, and ASP_DAC 2008.

He received the Most Excellent Design Award, and Special Feature Award in the University Design Contest in the ASP-DAC 1997 and 1998, respectively. He received the Best Paper Awards in the 36th DAC held in New Orleans, LA in 1999; in the 10th ICSPAT, Orlando, FL in 1999; and in the ICCD Austin, TX in 1999. In 2000, he received National Medal from Korean government for his contribution to research and education in IC design. He is a member of National Academy of Engineering Korea(NAEK), and Korean Academy of Science and Technology(KAST).. He is a Fellow of IEEE.

 

Sungjoo Yoo is currently an assistant professor at Department of EE, POSTECH, Korea. He received Ph.D. from Seoul National Univ. in 2000. He worked as researcher at TIMA laboratory, Grenoble France from 2000 to 2004. He was also with Samsung System LSI from 2004 to 2008, where he led system-on-chip architecture design team and was involved in architecture designs for mobile application processors and solid state disk. His research interests include software, architecture and RTL design for lowpower SoC, and memory and storage hierarchy from cache, DRAM, phase-change RAM to solid state disk. He received Best Paper Award at International SoC Conference (ISOCC) in 2006 and Best Paper nominations at Design Automation Conference (DAC) in 2011 and Design Automation and Test in Europe (DATE) in 2002 and 2009.