Electronic Packaging: Design, Materials, Process, and Reliability

Intended to be an electronic packaging resource, this text features writing from four leaders in the the four intertwined disciplines of packaging. Recent technological advances are discussed, including BGA, Flip Chip and CSP.

John H. Lau received his Ph.D. degree in Theoretical and Applied Mechanics from the University of Illinois (1977), a M.A.Sc. degree in Structural Engineering from the University of British Columbia (1973), a second M.S. degree in Engineering Physics from the University of Wisconsin (1974), and a third M.S. degree in Management Science from Fairleigh Dickinson University (1981). He also has a B.E. degree in Civil Engineering from National Taiwan University (1970). John is an interconnection technology scientist at Agilent Technologies, Inc. His current interests cover a broad range of electronic and optoelectronic packaging and manufacturing technology. Prior to Agilent, he worked for Express Packaging Systems, Hewlett-Packard Company, Sandia National Laboratory, Bechtel Power Corporation, and Exxon Production and Research Company. With more than 30 years of R&D and manufacturing experience in the electronics, petroleum, nuclear, and defense industries, he has given over 200 workshops, authored and co-authored over 180 peer reviewed technical publications, and is the author and editor of 13 books: Solder Joint Reliability; Handbook of Tape Automated Bonding; Thermal Stress and Strain in Microelectronics Packaging; The Mechanics of Solder Alloy Interconnects; Handbook of Fine Pitch Surface Mount Technology; Chip On Board Technologies for Multichip Modules; Ball Grid Array Technology; Flip Chip Technologies; Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies; Electronics Packaging: Design, Materials, Process, and Reliability; Chip Scale Package (CSP): Design, Materials, Process, Reliability, and Applications; Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, and Microvias for Low Cost, High Density Interconnects. John served as one of the associate editors of the IEEE Transactions on Components, Packaging, and Manufacturing Technology and ASME Transactions, Journal of Electronic Packaging. He also served as general chairman, program chairman, and session chairman, and invited speaker of several IEEE, ASME, ASM, MRS, IMAPS, SEMI, and SMI International conferences. He received a few awards from ASME and IEEE for best papers and outstanding technical achievements, and is an ASME Fellow and an IEEE Fellow. He is listed in American Men and Women of Science and Who’s Who in America.

C. P. Wong is a Regents’ Professor (the highest ranking distinguished Professor at Georgia Tech) at the School of Materials Science and Engineering and a Research Director at the NSF Packaging Research Center at Georgia Institute of Technology. He received his B.S. degree in chemistry from Purdue University, and his Ph.D. degree in chemistry from Pennsylvania State University. Thereafter, he was awarded a two-year Postdoctoral Fellowship at Stanford University with Nobel Laureate Prof. Henry Taube. Dr. Wong spent 19 years at AT&T Bell Labs and was elected as a Bell Labs Fellow(the most prestigious Award bestowed by AT&T Bell Labs) in 1992. His research interests lie in the fields of polymeric materials, reaction mechanism, IC encapsulation, in particular, hermetic equivalent plastic packaging, electronic packaging processes, interfacial adhesions, PWB, SMT assembly and component reliability. He received many awards, among those, the AT&T Bell Laboratories Distinguished Technical Staff Award in 1987, the AT&T Bell Labs Fellow Award in 1992, the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society Outstanding and Best Paper Awards in 1990, 1991, 1994, 1996 and 1998, the IEEE Technical Activities Board Distinguished Award in 1994, the 1995 IEEE CPMT Society’s Outstanding Sustained Technical Contribution Award, the 1999 Georgia Tech’s Outstanding Faculty Research Program Development Award, the 1999 NSF-Packaging Research Center Faculty of the Year Award, the Georgia Tech Sigma Xi Faculty Best Research Paper Award in 2000 and the University Press (London, UK) Award of Excellence in 2000. He holds over 45 U.S. patents, numerous international patents, and over 270 technical papers in the related area. For the past five years since joining Georgia Tech, he has been a Research Director at the world renowned NSF electronic Packaging Center. Leading a team of 32 faculty from six departments and 270 graduate students from Georgia Tech. Besides, he also works with over sixty United States, Japan, and European major semiconductor companies providing a leadership role in technology transfer. Dr. Wong was elected a member of the National Academy of Engineering in 2000, and he is a Fellow of the IEEE, AIC and AT&T Bell Labs, and was the general chairman of the IEEE/EIA 41st Electronic Components and Technology Conference in 1991. He served as the technical vice president (1990 & 1991), and the president (1992 & 1993) of the IEEE-CPMT Society, member of the IEEE TAB management committee in 1993-94, chair of the IEEE TAB Design and Manufacturing Engineering in 1995-97 and the IEEE Nomination and Appointment committee in 1996-97.