Digital Logic Design Using Verilog: Coding and RTL Synthesis

Taraate, Vaibbhav

ISBN 10: 9811632014 ISBN 13: 9789811632013

Editorial: Springer, 2022

Idioma: Ingl�s

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Detalles bibliogr�ficos

T�tulo

Digital Logic Design Using Verilog: Coding and RTL Synthesis

Editor

Springer

Fecha de publicaci�n

2022

Idioma

Ingl�s

ISBN 10

9811632014

ISBN 13

9789811632013

Encuadernaci�n

Encuadernaci�n de tapa blanda

Edici�n

2� Edici�n

Estado

New

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Sinopsis

This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.

Acerca del autor

Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

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