Digital Design and Modeling with VHDL and Synthesis (Systems)

The author focuses on the ultimate product of the design cycle: the implementation of a digital design. VHDL coding, synthesis methodologies and verification techniques are presented as tools to support the final design implementation. Readers will understand how to apply and adapt techniques for VHDL coding, verification, and synthesis to various situations.

Digital Systems Design with VHDL and Synthesis is a result of K.C. Chang's practical experience in both design and as an instructor. Many of the design techniques and considerations illustrated throughout the chapters are examples of viable designs. His teaching experience leads to a step-by-step presentation that addresses common mistakes and hard-to-understand concepts in a way that eases learning.

Unique features of the book include the following:

• VHDL code explained line by line to capture the logic behind the design concepts
• VHDL is verified using VHDL test benches and simulation tools
• Simulation waveforms are shown and explained to verify design correctness
• VHDL code is synthesized and commands and strategies are discussed. Synthesized schematics and results are analyzed for area and timing
• Variations on the design techniques and common mistakes are addressed; Demonstrated standard cell, gate array, and FPGA three design processes
• Each with a complete design case study
• Test bench, post-layout verification, and test vector generation processes.

Practical design concepts and examples are presented with VHDL code, simulation waveforms, and synthesized schematics so that readers can better understand their correspondence and relationships.