This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Num Pages: 278 pages, 65 black & white illustrations, 79 colour illustrations, 12 black & white tables, biograp. BIC Classification: TJFC; UYF. Category: (P) Professional & Vocational. Dimension: 241 x 167 x 21. Weight in Grams: 556. . 2013. 2014th Edition. Hardcover. . . . .

N� de ref. del art�culo V9781461442738

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Detalles bibliogr�ficos

T�tulo: Designing 2D and 3D Network-on-chip Architectures
Editor: Springer-Verlag New York Inc.
Fecha de publicaci�n: 2013
Idioma: Ingl�s
ISBN 10: 1461442737
ISBN 13: 9781461442738
Encuadernaci�n: Encuadernaci�n de tapa dura
Estado: New

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Sinopsis

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

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This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty. Case studies are used to illuminate new design methodologies.

� Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect;

� Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance;

� Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management.

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