Designing 2D and 3D Network-on-Chip Architectures

Konstantinos Tatas, et al.

ISBN 10: 1461442737 ISBN 13: 9781461442738

Editorial: Springer-Verlag Publishing, 2013

Idioma: Ingl�s

Condici�n: Usado - Como Nuevo Encuadernaci�n de tapa dura

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Descripci�n

Fine/As New; Semi-Flexible Covers; This book is brand new and still sealed in the publisher's original shrinkwrap; Perfect, new condition; This book will be stored and delivered in a sturdy cardboard box with foam padding; Medium Format (8.5" - 9.75" tall); Red and purple covers with title in white lettering; 2013, Springer-Verlag Publishing; 265 pages; "Designing 2D and 3D Network-on-Chip Architectures," by Konstantinos Tatas, et al.

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Detalles bibliogr�ficos

T�tulo: Designing 2D and 3D Network-on-Chip Architectures
Editor: Springer-Verlag Publishing
Fecha de publicaci�n: 2013
Idioma: Ingl�s
ISBN 10: 1461442737
ISBN 13: 9781461442738
Encuadernaci�n: Encuadernaci�n de tapa dura
Estado: Like New

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Sinopsis

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

De la contraportada

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty. Case studies are used to illuminate new design methodologies.

� Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect;

� Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance;

� Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management.

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Salish Sea Books
WA, U.S.A.

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Thank you for taking an interest in one of our books. We are a mail-order only bookstore located in Bellingham, WA specializing in modern out-of-print books of all genres.

If you are an international customer, we ship internationally by UPS Worldwide Expedited. The average delivery time is 1 to 2 weeks, and each shipment can be fully tracked at www.ups.com. For international shipments, it is important to provide a valid phone number with your order. Most international shipments are delivered wit...

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