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Detalles bibliogr�ficos

T�tulo: The DLX Instruction Set Architecture Handbook
Editor: Morgan Kaufmann (edition 1)
Fecha de publicaci�n: 1995
Idioma: Ingl�s
ISBN 10: 1558603719
ISBN 13: 9781558603714
Encuadernaci�n: Paperback
Edici�n: 1.
Estado: Good

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Sinopsis

The definitive source for the DLX instruction set architecture introduced in John L. Hennessy and David A. Patterson's Computer Architecture: A Quantitative Approach. DLX is a selective amalgam of several sophisticated load/store architectures; it was developed to serve as a simple example of a pure RISC architecture and is invoked throughout Computer Architecture to demonstrate design principles. With its complete and up-to-date information on the details of DLX, this handbook is a valuable supplement for anyone studying from Computer Architecture, whether self-taught or as part of a class. It will also make an informative addition to the library of any computer systems designer or RISC aficionado. Beginning with the origins and history of DLX, the opening section of the handbook covers the essential topics of registers, data formats, addressing, and interrupt handling. The second section provides a general description of the instruction set architecture, followed by the specifics of DLX instruction types, format notation, and operation notation. Appendices provide a quick reference to the instruction set and the latest available version of documentation for the DLXsim simulator.

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David Kaeli received a BS and PhD in Electrical Engineering from Rutgers University, and an MS in Computer Engineering from Syracuse University. He is the Associate Dean of Undergraduate Programs in the College of Engineering and a Full Processor on the ECE faculty at Northeastern University, Boston, MA where he directs the Northeastern University Computer Architecture Research Laboratory (NUCAR). Prior to joining Northeastern in 1993, Kaeli spent 12 years at IBM, the last 7 at T.J. Watson Research Center, Yorktown Heights, NY.

Dr. Kaeli has co-authored more than 200 critically reviewed publications. His research spans a range of areas including microarchitecture to back-end compilers and software engineering. He leads a number of research projects in the area of GPU Computing. He presently serves as the Chair of the IEEE Technical Committee on Computer Architecture. Dr. Kaeli is an IEEE Fellow and a member of the ACM.

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