A Comprehensive Treatise on Chip Design and Semiconductor Fabrication (Paperback)
Idioma: inglés
Editorial: Independently Published, 2026
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Paperback. There is a persistent and forgivable belief among students that the integrated circuit is a solved problem - that somewhere a machine takes in a design and returns a chip, and that the interesting questions lie elsewhere. This book exists because that belief is wrong in an instructive way. The modern semiconductor is the most intricate object that human beings manufacture, and it is intricate not in one dimension but in five or six simultaneously: in quantum mechanics, in chemistry, in optics, in mechanical engineering, in computer science, in economics, and in the industrial logistics that bind them together. A single logic die may contain more than fifty billion transistors, each of which must work; it is patterned by light of a wavelength shorter than most X-rays used in dentistry; it is assembled from more than a thousand discrete process steps in a room where a single particle of dust larger than a virus can destroy the product; and the factory that makes it costs more than an aircraft carrier.The purpose of this volume is to present that whole enterprise as a single connected argument. Books on VLSI design tend to stop at the tape-out boundary and treat fabrication as a black box characterised by a design-rule manual. Books on semiconductor processing tend to begin at the wafer and treat the design as an arbitrary pattern arriving on a mask. Both halves are taught well; the seam between them is taught badly. Yet almost every difficult problem in the industry today lives precisely on that seam. Why must a designer restrict layout to unidirectional metal on a single pitch? Because of what a lithographic scanner can resolve. Why does a synthesis tool refuse to reduce area below a floor? Because of what patterning and variability will actually yield. Why did the industry abandon planar transistors, then abandon the fin? Because electrostatics at short channel lengths dictated it, and because processing had, at last, learned how to build the alternative. To understand any of these decisions, one must be able to move fluently between the abstraction levels - and the ability to move between levels is precisely what this book tries to teach.Who this book is for. The primary audience is the advanced undergraduate or beginning graduate student in electrical engineering, electronic engineering, computer engineering, materials science, or applied physics, who has completed an introductory course in electronic devices and one in digital logic. How the book is organised. The volume is divided into four parts and twenty-one chapters. Part I establishes foundations: the historical and economic logic of integration, the solid-state physics of semiconductors, and the structure and behaviour of the MOS transistor. Part II treats design: CMOS circuit families, the digital implementation flow from specification through synthesis and verification, physical design, timing and signal-integrity closure, low-power methodology, analog and mixed-signal circuits, and memory. Part III treats fabrication: crystal growth and wafer preparation, thermal and deposition processes, photolithography, etching and doping, interconnect and planarisation, and the integration discipline that binds several hundred unit steps into a working process. Part IV treats what happens after the wafer is finished and why any of it is economically possible: test, yield and reliability; packaging and advanced heterogeneous integration; the industrial and economic structure of the sector; and the technical frontiers now under active development. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability.…
N° de ref. del artículo 9798188344672
- Título
- A Comprehensive Treatise on Chip Design and Semiconductor Fabrication (Paperback)
- Autor
- Harmeet Singh
- Editorial
- Independently Published
- Año de publicación
- 2026
- Estado
- new
- Encuadernación
- Paperback
- Idioma
- inglés
- ISBN 13
- 9798188344672
The purpose of this volume is to present that whole enterprise as a single connected argument. Books on VLSI design tend to stop at the tape-out boundary and treat fabrication as a black box characterised by a design-rule manual. Books on semiconductor processing tend to begin at the wafer and treat the design as an arbitrary pattern arriving on a mask. Both halves are taught well; the seam between them is taught badly. Yet almost every difficult problem in the industry today lives precisely on that seam. Why must a designer restrict layout to unidirectional metal on a single pitch? Because of what a lithographic scanner can resolve. Why does a synthesis tool refuse to reduce area below a floor? Because of what patterning and variability will actually yield. Why did the industry abandon planar transistors, then abandon the fin? Because electrostatics at short channel lengths dictated it, and because processing had, at last, learned how to build the alternative. To understand any of these decisions, one must be able to move fluently between the abstraction levels — and the ability to move between levels is precisely what this book tries to teach.
Who this book is for. The primary audience is the advanced undergraduate or beginning graduate student in electrical engineering, electronic engineering, computer engineering, materials science, or applied physics, who has completed an introductory course in electronic devices and one in digital logic.
How the book is organised. The volume is divided into four parts and twenty-one chapters. Part I establishes foundations: the historical and economic logic of integration, the solid-state physics of semiconductors, and the structure and behaviour of the MOS transistor. Part II treats design: CMOS circuit families, the digital implementation flow from specification through synthesis and verification, physical design, timing and signal-integrity closure, low-power methodology, analog and mixed-signal circuits, and memory. Part III treats fabrication: crystal growth and wafer preparation, thermal and deposition processes, photolithography, etching and doping, interconnect and planarisation, and the integration discipline that binds several hundred unit steps into a working process. Part IV treats what happens after the wafer is finished and why any of it is economically possible: test, yield and reliability; packaging and advanced heterogeneous integration; the industrial and economic structure of the sector; and the technical frontiers now under active development.
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