Sinopsis
Building testbenches is a complex task requiring both hardware and
software skills. Next Level Testbenches: Design Patterns in
SystemVerilog and UVM delves into testbench construction from a
software perspective. The book explores classic software design
patterns and their implementation in SystemVerilog. It also explores
patterns that are specific to UVM testbench construction.
Fully working code examples accompany all of the descriptions of the
patterns. Topaz, a companion library available at GitHub, contains
complete, functioning examples.
Next Level Testbenches is essential reading for practicing
verification engineers engaged in testbench development in
SystemVerilog and UVM.
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