ASIC Design and Synthesis: RTL Design Using Verilog - Tapa dura

Taraate, Vaibbhav

 
9789813346413: ASIC Design and Synthesis: RTL Design Using Verilog
Tapa dura
ISBN 10: 9813346418 ISBN 13: 9789813346413
Editorial: Springer, 2021

Sinopsis

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

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Acerca del autor

Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog , VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.


De la contraportada

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.?

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Editorial
Springer
Año de publicación
2021
Idioma
Inglés
ISBN 10 
9813346418
ISBN 13 
9789813346413
Encuadernación
Tapa dura
Número de edición
1
Número de páginas
354
Contacto del fabricante
no disponible
Persona responsable
CMN Printpool Inh. Mathis Neumann
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Hamburg
Alemania

Otras ediciones populares con el mismo título

9789813346444: ASIC Design and Synthesis: RTL Design Using Verilog

Edición Destacada

ISBN 10:  9813346442 ISBN 13:  9789813346444
Editorial: Springer, 2022
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