Digital Logic Design Using Verilog: Coding and RTL Synthesis - Tapa dura

Taraate, Vaibbhav

 
9789811631986: Digital Logic Design Using Verilog: Coding and RTL Synthesis
Tapa dura
ISBN 10: 9811631980 ISBN 13: 9789811631986
Editorial: Springer, 2021

Sinopsis

This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists. 

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Acerca del autor

Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

De la contraportada

This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.

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Editorial
Springer
Año de publicación
2021
Idioma
Inglés
ISBN 10 
9811631980
ISBN 13 
9789811631986
Encuadernación
Tapa dura
Número de edición
2
Número de páginas
632
Contacto del fabricante
no disponible
Persona responsable
CMN Printpool Inh. Mathis Neumann
https://www.also.com/ec/cms5/en_6000/6000/index.jsp

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Hamburg
Alemania

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9789811632013: Digital Logic Design Using Verilog: Coding and RTL Synthesis

Edición Destacada

ISBN 10:  9811632014 ISBN 13:  9789811632013
Editorial: Springer, 2022
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