Logic Synthesis and SOC Prototyping: RTL Design using VHDL - Tapa blanda

Taraate, Vaibbhav

 
9789811513169: Logic Synthesis and SOC Prototyping: RTL Design using VHDL
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ISBN 10: 9811513163 ISBN 13: 9789811513169
Editorial: Springer-Verlag GmbH, 2021

Sinopsis

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design.

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Acerca del autor

Vaibbhav Taraate is Entrepreneur and Mentor at “1 Rupee S T”. He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 years ofexperience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

De la contraportada

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.


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Editorial
Springer-Verlag GmbH
Año de publicación
2021
Idioma
Inglés
ISBN 10 
9811513163
ISBN 13 
9789811513169
Encuadernación
Tapa blanda
Número de edición
1
Número de páginas
270
Contacto del fabricante
ProductSafety@springernature.com
ProductSafety@springernature.com

Poststr. 9
Darmstadt
64293
Alemania

Otras ediciones populares con el mismo título

9789811513138: Logic Synthesis and SOC Prototyping: RTL Design using VHDL

Edición Destacada

ISBN 10:  9811513139 ISBN 13:  9789811513138
Editorial: Springer-Verlag GmbH, 2020
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