Artículos relacionados a High-level Estimation and Exploration of Reliability...
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Computer Architecture and Design Methodologies) - Tapa blanda
Sinopsis
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
"Sinopsis" puede pertenecer a otra edición de este libro.
Acerca del autor
Dr.-Ing. Zheng Wang earned the Bachelor degree in physics from Shanghai Jiao Tong University (SJTU), China and Master degree in Electronic Engineering from Technische Universität München (TUM), Germany. From 2008 till 2009, he worked in the mobile sector of Infineon Technologies AG in Munich (currently Intel Mobile Communications). In 2010 he joined as a research associate in the Institute for Communication Technologies and Embedded Systems (ICE) of RWTH-Aachen University, Germany, where he obtained the PhD (Dr.-Ing.) in the year 2015. From 2015 till 2016, he worked in the Bio-inspired Reconfigurable Analog INtegrated (BRAIN) Systems Lab, Nanyang Technological University, Singapore in the field of neuromorphic ASIC and hardware security. In 2017 he joined the Center for Automotive Electronics, Shenzhen Institutes of Advanced Technology as an Assistant Professor.
Dr.-Ing. Wang's research interests include the design of digital processor and system, low-power and error-resilient architecture, hardware platform of neuromorphic computing. During PhD, he has published 20+ papers in well-known international conferences (e.g. DAC, DATE, GLSVLSI, ISCAS, ISQED). The reliability-aware high-level synthesis tool flow developed by him was demonstrated in DAC'13 and DAC'14. He has participated several international research projects funded by European Union, German Research Foundation, and Singaporean and Chinese grant agencies. He has successfully taped-out one mixed-signal Extreme Learning Machine (ELM) processor with 65nm CMOS technology, which achieves the peak performance of 1.2TOPS/W.
De la contraportada
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
"Sobre este título" puede pertenecer a otra edición de este libro.
- EditorialSpringer
- Año de publicación2018
- ISBN 10 9811093210
- ISBN 13 9789811093210
- EncuadernaciónTapa blanda
- IdiomaInglés
- Número de páginas220
- Contacto del fabricanteno disponible
Comprar nuevo
Ver este artículo
EUR 92,27
EUR 19,49 gastos de envío desde Alemania a España
Destinos, gastos y plazos de envíoOtras ediciones populares con el mismo título
Resultados de la búsqueda para High-level Estimation and Exploration of Reliability...
Imagen de archivo
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip.
Publicado por
Singapore, Springer., 2018
ISBN 10: 9811093210
ISBN 13: 9789811093210
Antiguo o usado
Tapa blanda
Librería: Universitätsbuchhandlung Herta Hold GmbH, Berlin, Alemania
Calificación del vendedor: 4 de 5 estrellas
XX, 197 p. Softcover. Versand aus Deutschland / We dispatch from Germany via Air Mail. Einband bestoßen, daher Mängelexemplar gestempelt, sonst sehr guter Zustand. Imperfect copy due to slightly bumped cover, apart from this in very good condition. Stamped. Computer Architecture and Design Methodologies. Sprache: Englisch. Nº de ref. del artículo: 9099GB
Cantidad disponible: 1 disponibles
Imagen de archivo
High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip
Librería: ThriftBooks-Dallas, Dallas, TX, Estados Unidos de America
Calificación del vendedor: 5 de 5 estrellas
Paperback. Condición: Good. No Jacket. Pages can have notes/highlighting. Spine may show signs of wear. ~ ThriftBooks: Read More, Spend Less 0.69. Nº de ref. del artículo: G9811093210I3N00
Cantidad disponible: 1 disponibles
Imagen del vendedor
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Librería: moluna, Greven, Alemania
Calificación del vendedor: 5 de 5 estrellas
Condición: New. Nº de ref. del artículo: 449935451
Cantidad disponible: Más de 20 disponibles
Imagen del vendedor
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Publicado por
Springer Nature Singapore Mai 2018, 2018
ISBN 10: 9811093210
ISBN 13: 9789811093210
Nuevo
Taschenbuch
Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. 220 pp. Englisch. Nº de ref. del artículo: 9789811093210
Cantidad disponible: 2 disponibles
Imagen de archivo
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Computer Architecture and Design Methodologies)
Librería: Ria Christie Collections, Uxbridge, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Condición: New. In. Nº de ref. del artículo: ria9789811093210_new
Cantidad disponible: Más de 20 disponibles
Imagen del vendedor
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Publicado por
Springer Nature Singapore, Springer Nature Singapore, 2018
ISBN 10: 9811093210
ISBN 13: 9789811093210
Nuevo
Taschenbuch
Librería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. Nº de ref. del artículo: 9789811093210
Cantidad disponible: 1 disponibles
Imagen del vendedor
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Publicado por
Springer Nature Singapore, Springer Nature Singapore Mai 2018, 2018
ISBN 10: 9811093210
ISBN 13: 9789811093210
Nuevo
Taschenbuch
Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. Neuware -This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 220 pp. Englisch. Nº de ref. del artículo: 9789811093210
Cantidad disponible: 2 disponibles
Imagen de archivo
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Computer Architecture and Design Methodologies)
Librería: Books Puddle, New York, NY, Estados Unidos de America
Calificación del vendedor: 4 de 5 estrellas
Condición: New. pp. 217. Nº de ref. del artículo: 26380924405
Cantidad disponible: 4 disponibles
Imagen de archivo
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Computer Architecture and Design Methodologies)
Impresión bajo demandaLibrería: Majestic Books, Hounslow, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Condición: New. Print on Demand pp. 217. Nº de ref. del artículo: 381931050
Cantidad disponible: 4 disponibles
Imagen de archivo
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Computer Architecture and Design Methodologies)
Librería: Revaluation Books, Exeter, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Paperback. Condición: Brand New. reprint edition. 197 pages. 9.25x6.10x0.47 inches. In Stock. Nº de ref. del artículo: x-9811093210
Cantidad disponible: 2 disponibles