Emerging Technologies and Circuits: 66 (Lecture Notes in Electrical Engineering, 66) - Tapa dura

Sinopsis

Foreword. I. INTRODUCTION. Synergy between design and technology; Michel Brillouët. II. EMERGING TECHNOLOGY AND DEVICES. New state variable opportunities beyond CMOS: a system perspective; Victor V. Zhirnov, Ralph K. Cavin, George I. Bourianoff. A simple compact model to analyze he impact of ballistic and quasi-ballistic transport on ring oscillator performance; S. Martinie, D. Munteanu, G. Le Carval, J.L. Autran. III. ADVANCED DEVICES AND CIRUITS. Low-voltage scaled 6T FinFET SRAM cells; N. Collaert, K. von Arnim, R. Rooyackers, T. Vandeweyer, A. Mercha, B. Parvais, L. Witters, A. Nackaerts, E. Altamirano Sanchez, M. Demand, A. Hikavyy, S. Demuynck, K. Devriendt, F. Bauer, I. Ferain, A. Veloso, K. De Meyer, S. Biesemans, M. Jurczak. Independent-double-gate FinFET SRAM cell for drastic leakage current reduction; Kazuhiko Endo, Shin-ichi O'uchi, Yuki Ishikawa, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Meishoku Masahara, Junichi Tsukada, Kenichi Ishii, Eiichi Suzuki . Metal gate effects on a 32 nm metal gate resistor; Thuy Dao, Ik_Sung Lim, Larry Connell, Dina H. Triyoso, Youngbog Park, Charlie Mackenzie. IV. RELIABILITY AND SEU. Threshold voltage shift instability induced by plasma charging damage in MOSFETs with High-k dielectric; Koji Eriguchi, Masayuki Kamei, Kenji. Okada, Hiroaki Ohta, Kouichi Ono. Analysis of Si substrate damage induced by inductively coupled plasma reactor with various superposed bias frequencies; Y. Nakakubo, A. Matsuda, M. Kamei, H. Ohta, K. Eriguchi, K. Ono. V. POWER, TIMING AND VARIABILITY. CMOS SOI technology for WPAN. Application to 60 GHz LNA; A.Siligaris, C.Mounet, B.Reig, P. Vincent, A.Michel. SRAM memory cell leakage reduction design techniques in 65nm low power PD-SOI CMOS; Olivier Thomas, Marc Belleville, Richard Ferrant. Resilient circuits for dynamic variation tolerance; Keith A. Bowman, James W.Tschanz. Process variability-induced timing failures - A challenge in nanometer CMOS low-power design; Xiaonan Zhang, Xiaoliang Bai. How does inverse temperature dependence affect timing sign-off; Sean H. Wu, Alexander Tetelbaum, Li-C. Wang. CMOS Logic Gates Leakage Modeling Under Statistical Process Variations; Carmelo D'Agostino, Philippe Flatresse, Edith Beigne, Marc Belleville. On-chip circuit technique for measuring jitter and skew with picosecond resolution; K. A Jenkins, Z. Xu, A.P. Jose, K.L. Shepard. VI. ANALOG AND MIXED SIGNAL. DC-DC converter technologies for on-chip distributed power supply systems - 3D stacking and hybrid operation; Kohei Onizuka, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai. Sampled analog signal processing: from software-defined to software radio; François RIVET, André MARIANO, Yann DEVAL, Dominique DALLET, Jean-Baptiste BEGUERET, Didier BELOT.

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