Language:Chinese.paperback.Pub Date:2024-09.publisher:People's Posts and Telecommunications Publishing House.description:Paperback. Pub Date: 2024-09 Pages: 294 Publisher: Posts & Telecom Press This book systematically explains the language rules and syntax of Verilog HDL. based on the Verilog-2001 and Verilog-2005 language standards. providing comprehensive and accura
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Librería: liu xing, Nanjing, JS, China
paperback. Condición: New. Paperback. Pub Date: 2024-09 Pages: 294 Publisher: Posts & Telecom Press This book systematically explains the language rules and syntax of Verilog HDL. based on the Verilog-2001 and Verilog-2005 language standards. providing comprehensive and accurate knowledge points. The main contents include an introduction to Verilog HDL. data types. expressions. gate-level and switch-level modeling. dataflow modeling. behavioral modeling. hierarchical structures. tasks and functions. TestBench testing a. Nº de ref. del artículo: DT047857
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