现代应用集成电路设计(Modern ASIC Design)(英文版)[WX]周电科学出版社9787030317667 - Tapa blanda

Modern applications of information science and technology. integrated circuit design series of academic works

paperback. Condición: New. Ship out in 2 business day, And Fast shipping, Free Tracking number will be provided after the shipment.Pages Number: 394 Publisher: Science Pub. Date :2011-07-01 version 1. Modern integrated circuits design (English). Zhou Dian-based author of ten years at American University professor. Application of modern integrated circuit design course collate manuscripts from the main contents include ASIC design flow. design specifications defined and standardized. logic circuit design. physical design. timing analysis and power performance verification testing. Readers need to have digital integrated circuits and hardware description language (VHDL) the basics. According to the specific curriculum requirements. the book can be used for a semester of teaching content. including the application of integrated circuit design process. design specifications defined and standardized. logic design and physical design. Issues on the forefront of integrated circuit development. the book in Chapters 7 and 8 in the back describes the research as the basis of knowledge. Modern integrated circuits design (English) electronic and computer work as a professional college senior or graduate teaching. but also for integrated circuit design professionals reference reading. Contents: PrefaceChapter 1Introduction1.1History of Integrated Circuits1.2Roadmap of IC Technology1.3ASIC1.4Design Flow1.5CAD Tools1.6AnASIC Design Project MSDAP1.7How to Use This Book1.8Summery1.9ProblemsReferencesChapter 2VLSI Design Perspective and Flow2.1Introduction2.2VLSI Technology Trend2.3SoC2 .4 Methodology for Custom and Semi-custom IC Design2.4.1Gate array2.4.2Standard cell2.4.3FPGA2.5Design Domain and Perspective2.6Design Flow2.7Design Task2.8Summary2.9ProblemsReferencesChapter 3Specification Development3.1Introduction3.2AnASIC Project MSDAP3.3An Overall View of the Specific Requirement3.3.1The required computation method by the MSDAP3.3.2Additional information for the specification3.4The System Setting3.5IO Interface and Pins3.5.1Pins and their assignments3.5.2Signal format and waveform3.6Other Issues of the Specification3.7Summary3.8ProblemsReferencesChapter 4Architecture Design4.1Introduction4.2Datapath Structure4.2.1Single processor sequential structure4.2.2Multi-processor parallel structure4.3Functional Blocks and IPs4.3.1IP core4.3.2 Functional blocks in the MSDAP architecture4.4 Time Budget and Scheduling4.5A Sample Architecture of the MSDAP Project4 .5.1 An architecture sample4.5.2Time budget justification of the proposed architecture4.6Summary4.7ProblemsReferencesChapter 5Logic and Circuit Design5.1Introduction5.2Combinational Logics5.2.1Decoder5.2.2Encoder5.2.3Multiplexer5.2.4Arithmetic logic blocks5.3Sequential Logics5.3.1Latch and flip- flop5.3.2Shift register5.3.3Counter5.3.4 FSM5.4Datapath5.5Asynchronous Circuit5.6Summery5.7ProblemsReferencesChapter 6Physical Design6.1Introduction6.2Design Rules6.3Floorplan6.4Routing6.4.1Global routing6.4.2Local routing6.5Physical Layout Verification6.5.1DRC6.5.2 XOR check6 .5.3 Antenna check6.5.4 ERC6.5.5LVS check6.6Clock Network6.7Power Network6.8Engineering Change Order6.9Package6.10Summary6.11ProblemsReferencesChapter 7Timing. Power. and Performance Analysis7.1Introduction7.2Buffer Insertion Mechanism7.3Transistor and Gate Sizing7.3.1Transistor sizing7. 3.2Buffer sizing7.3.3Gate sizing7.4Timing Analysis7.4.1Static timing analysis7.4.2DTA vs. STA7.4.3Circuit simulation in STA7.5Interconnect Model and Circuit Order Reduction7.5.1Lumped RC vs. distributed RLC model7.5.2Circuit order reduction7.6Low Power Design7.7Design for Manufacture7.8High-level Synthesis7.9Performance Bound Evaluation7.10Summary7.11ProblemsReferencesChapter 8Verification and Testing8.1Introduction8.2Digital Circuits Test8.2.1Fault modeling8.2.2Fault simulation8.2.3Test generation for combinational logic8.2.4Test generation for sequential logic8 .2.5 ATPG using TetraMAX8.3BIST8.3.1The concept of BIST8.3.2TPG8.3.3ORA8.3.4BIST architectures8.4Scan and Bounda. Nº de ref. del artículo: LJ1631

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