Artículos relacionados a HIGH RESOLUTION AND LOW JITTER FULL CUSTOM ADPLL ARCHITECTUR...

HIGH RESOLUTION AND LOW JITTER FULL CUSTOM ADPLL ARCHITECTURES: FOR FREQUENCY SYNTHESIZER IP - Tapa blanda

Jahangir, Mohd Ziauddin; Shekar, P. Chandra

 
9786208445584: HIGH RESOLUTION AND LOW JITTER FULL CUSTOM ADPLL ARCHITECTURES: FOR FREQUENCY SYNTHESIZER IP
Tapa blanda
ISBN 10: 6208445582 ISBN 13: 9786208445584
Editorial: LAP LAMBERT Academic Publishing, 2025

Sinopsis

All digital PLLs are being considered as an effective replacement due to high immunity of digital circuits to PVT variations. However, ADPLLs suffer from the problem of low resolution and high jitter/ phase noise apart from fundamental problems of complex design procedures. It was found through literature surveys and experimental verifications that there are still some challenges related to resolution, jitter/phase noise that need to be addressed, in the existing ADPLLs. Similarly, it was also found that there is a shortcoming in the models used to describe ADPLLs. In this regard, an extensive classification of existing ADPLL architectures was made. Some of the architectures found in literature were critically examined by redesigning and simulation verification at various levels of design with a wide set of simulation/emulation tools. Comparative analysis was done and shortcomings in each architecture were critically identified. Methods to improve resolution and phase noise were proposed and verified using simulation.

"Sinopsis" puede pertenecer a otra edición de este libro.

Editorial
LAP LAMBERT Academic Publishing
Año de publicación
2025
Idioma
Inglés
ISBN 10 
6208445582
ISBN 13 
9786208445584
Encuadernación
Tapa blanda
Número de páginas
216
Contacto del fabricante
no disponible
Persona responsable
no disponible