TESTING OF eSRAM USING MMC- Algorithm And Parasitic Extraction Method - Tapa blanda

Parvathi, Muddapu; Vasantha, N.; Satya Prasad, K.

 
9786202095464: TESTING OF eSRAM USING MMC- Algorithm And Parasitic Extraction Method
Tapa blanda
ISBN 10: 6202095466 ISBN 13: 9786202095464
Editorial: LAP LAMBERT Academic Publishing, 2017

Sinopsis

The intention of the book is to highlight core issues of current technology relevant to embedded SRAM, testing methods and need of new test requirements. The importance of March algorithms and in depth working including examples were clearly shown. The failures of existing March algorithms and hence the development of MMC- (Modified March C-) algorithm will increase the reader interest in exploring much more test algorithms required for e-SRAM. Above this, the testing method using Parasitic extraction of R & C developed using Cadence tools and Microwind is highlight of the investigations. The layout level parasitic extraction of R&C method was applied on all possible SRAM fault models using 'bridge/short' created in electrical circuit environment. Using parasitic memory effect, fault detection dictionary was an outcome this research in which each fault model behavior is highlighted in terms of R & C at different technology nodes. The chosen technology nodes are 90nm, 120nm, and 180nm. This method was extended to few two cell fault models and discussed on coupling faults.

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Reseña del editor

The intention of the book is to highlight core issues of current technology relevant to embedded SRAM, testing methods and need of new test requirements. The importance of March algorithms and in depth working including examples were clearly shown. The failures of existing March algorithms and hence the development of MMC- (Modified March C-) algorithm will increase the reader interest in exploring much more test algorithms required for e-SRAM. Above this, the testing method using Parasitic extraction of R & C developed using Cadence tools and Microwind is highlight of the investigations. The layout level parasitic extraction of R&C method was applied on all possible SRAM fault models using 'bridge/short' created in electrical circuit environment. Using parasitic memory effect, fault detection dictionary was an outcome this research in which each fault model behavior is highlighted in terms of R & C at different technology nodes. The chosen technology nodes are 90nm, 120nm, and 180nm. This method was extended to few two cell fault models and discussed on coupling faults.

Biografía del autor

Dr. M. Parvathi,having 17 years of teaching experience, presently working as Professor in BVRITH College of Engineering for Women, have done her B.tech (ECE) from NIT Warangal, and M. Tech from JNTU Hyderabad. She obtained her Ph.D degree in the area of VLSI design from JNTUK Kakinada, AP, India. She guided over 15 PG scholars and 40 UG projects.

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Editorial
LAP LAMBERT Academic Publishing
Año de publicación
2017
Idioma
Inglés
ISBN 10 
6202095466
ISBN 13 
9786202095464
Encuadernación
Tapa blanda
Número de páginas
252
Contacto del fabricante
no disponible
Persona responsable
no disponible