Sinopsis
This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.
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Low Power Asynchronous Logic design for Viterbi Decoders
Publicado por
LAP LAMBERT Academic Publishing Sep 2018, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
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Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation. 56 pp. Englisch. Nº de ref. del artículo: 9786139851294
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Low Power Asynchronous Logic design for Viterbi Decoders
Publicado por
LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
Nuevo
Paperback
Librería: Revaluation Books, Exeter, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Paperback. Condición: Brand New. 56 pages. 8.66x5.91x0.13 inches. In Stock. Nº de ref. del artículo: zk6139851297
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Low Power Asynchronous Logic design for Viterbi Decoders
Publicado por
LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
Nuevo
Tapa blanda
Librería: moluna, Greven, Alemania
Calificación del vendedor: 4 de 5 estrellas
Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sakthivel T. Kalavathi DeviDr T. Kalavathi Devi completed her UG and PG in GCT, Coimbatore. Her areas of interest include VLSI Design, low power circuits, electronics system design. She has published papers in reputed journals and in. Nº de ref. del artículo: 385874302
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Low Power Asynchronous Logic design for Viterbi Decoders
Publicado por
LAP LAMBERT Academic Publishing Sep 2018, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
Nuevo
Taschenbuch
Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Englisch. Nº de ref. del artículo: 9786139851294
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Low Power Asynchronous Logic design for Viterbi Decoders
Publicado por
LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
Nuevo
Taschenbuch
Librería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation. Nº de ref. del artículo: 9786139851294
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