Artículos relacionados a Digital PLL for Audio Applications: Based on ASIC Low...
Reseña del editor
In this project, Verilog HDL is used for the implementation due to its compatibility with pure digital hardware like FPGA's. The Digital PLL is simulated and verified on FPGA to experience its advantages. The circuit comprises of a phase detector, loop filter, Numerically Controlled Oscillator (NCO), and two clock dividers. The circuit was stabilized to produce the frequency in the audio frequency range of 9.7 KHz. This agreed with the classical phase-locked loop model for the system. The stable long-term frequency clock was verified on the FPGA to generate the required locking frequency. The DC logic synthesis and a new synopsis low power flow was experimented for back annotation and to obtain the maximum possible operating frequency and area, timing and power estimation.
Biografía del autor
Shesharaman K.N received the B.E. degree in Electronics and Communication Engineering from Visvesvaraya Technological University,Karnataka, India in 2005 and M.Sc[Engg.] degree in VLSI System Design from Coventry University,U.K in 2007. His present research is focused on Analog, Mixed mode VLSI design and Data Converters for Medical Applications
"Sobre este título" puede pertenecer a otra edición de este libro.
- EditorialLAP LAMBERT Academic Publishing
- Año de publicación2012
- ISBN 10 3848404516
- ISBN 13 9783848404513
- EncuadernaciónTapa blanda
- IdiomaInglés
- Número de páginas76
EUR 108,74
EUR 29,56 gastos de envío desde Reino Unido a Estados Unidos de America
Destinos, gastos y plazos de envíoComprar nuevo
Ver este artículo
EUR 49,00
EUR 23,00 gastos de envío desde Alemania a Estados Unidos de America
Destinos, gastos y plazos de envíoResultados de la búsqueda para Digital PLL for Audio Applications: Based on ASIC Low...
Imagen del vendedor
Digital PLL for Audio Applications
Publicado por
LAP LAMBERT Academic Publishing Feb 2012, 2012
ISBN 10: 3848404516
ISBN 13: 9783848404513
Nuevo
Taschenbuch
Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In this project, Verilog HDL is used for the implementation due to its compatibility with pure digital hardware like FPGA's. The Digital PLL is simulated and verified on FPGA to experience its advantages. The circuit comprises of a phase detector, loop filter, Numerically Controlled Oscillator (NCO), and two clock dividers. The circuit was stabilized to produce the frequency in the audio frequency range of 9.7 KHz. This agreed with the classical phase-locked loop model for the system. The stable long-term frequency clock was verified on the FPGA to generate the required locking frequency. The DC logic synthesis and a new synopsis low power flow was experimented for back annotation and to obtain the maximum possible operating frequency and area, timing and power estimation. 76 pp. Englisch. Nº de ref. del artículo: 9783848404513
Gastos de envío:
EUR 23,00
De Alemania a Estados Unidos de America
Destinos, gastos y plazos de envío
Cantidad disponible: 2 disponibles
Imagen del vendedor
Digital PLL for Audio Applications : Based on ASIC Low Power and FPGA flow
Publicado por
LAP LAMBERT Academic Publishing, 2012
ISBN 10: 3848404516
ISBN 13: 9783848404513
Nuevo
Taschenbuch
Librería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In this project, Verilog HDL is used for the implementation due to its compatibility with pure digital hardware like FPGA's. The Digital PLL is simulated and verified on FPGA to experience its advantages. The circuit comprises of a phase detector, loop filter, Numerically Controlled Oscillator (NCO), and two clock dividers. The circuit was stabilized to produce the frequency in the audio frequency range of 9.7 KHz. This agreed with the classical phase-locked loop model for the system. The stable long-term frequency clock was verified on the FPGA to generate the required locking frequency. The DC logic synthesis and a new synopsis low power flow was experimented for back annotation and to obtain the maximum possible operating frequency and area, timing and power estimation. Nº de ref. del artículo: 9783848404513
Gastos de envío:
EUR 28,65
De Alemania a Estados Unidos de America
Destinos, gastos y plazos de envío
Cantidad disponible: 1 disponibles
Imagen del vendedor
Digital PLL for Audio Applications
Publicado por
LAP LAMBERT Academic Publishing, 2012
ISBN 10: 3848404516
ISBN 13: 9783848404513
Nuevo
Kartoniert / Broschiert
Librería: moluna, Greven, Alemania
Calificación del vendedor: 5 de 5 estrellas
Kartoniert / Broschiert. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: K Narayanan ShesharamanShesharaman K.N received the B.E. degree in Electronics and Communication Engineering from Visvesvaraya Technological University,Karnataka, India in 2005 and M.Sc[Engg.] degree in VLSI System Design from Coven. Nº de ref. del artículo: 5519806
Gastos de envío:
EUR 48,99
De Alemania a Estados Unidos de America
Destinos, gastos y plazos de envío
Cantidad disponible: Más de 20 disponibles
Imagen de archivo
Digital PLL for Audio Applications: Based on ASIC Low Power and FPGA flow
Publicado por
LAP LAMBERT Academic Publishing, 2012
ISBN 10: 3848404516
ISBN 13: 9783848404513
Antiguo o usado
Paperback
Librería: dsmbooks, Liverpool, Reino Unido
Calificación del vendedor: 4 de 5 estrellas
Paperback. Condición: Like New. Like New. book. Nº de ref. del artículo: D7F7-3-M-3848404516-6
Gastos de envío:
EUR 29,56
De Reino Unido a Estados Unidos de America
Destinos, gastos y plazos de envío
Cantidad disponible: 1 disponibles