Low Power Digital Design using Asynchronous Logic: Moving towards clock-less design - Tapa blanda

Antony Jayasekar, Sathish Vimalraj

 
9783846518441: Low Power Digital Design using Asynchronous Logic: Moving towards clock-less design
Tapa blanda
ISBN 10: 3846518441 ISBN 13: 9783846518441
Editorial: LAP LAMBERT Academic Publishing, 2011

Sinopsis

The need for low power design is motivated by several factors, such as the emergence of portable systems, thermal considerations, reliability issues, and, most importantly, environmental concerns. Lots of power is wasted in an electronic device when the system is idle. This book introduces a new method of achieving low power by reducing the dependency of the clock signal in the design. It mainly focuses on obtaining low power by implementing asynchronous logic.

"Sinopsis" puede pertenecer a otra edición de este libro.

Reseña del editor

The need for low power design is motivated by several factors, such as the emergence of portable systems, thermal considerations, reliability issues, and, most importantly, environmental concerns. Lots of power is wasted in an electronic device when the system is idle. This book introduces a new method of achieving low power by reducing the dependency of the clock signal in the design. It mainly focuses on obtaining low power by implementing asynchronous logic.

Biografía del autor

This work on Low power digital design using asynchronous logic is my first publication. I did this work as a thesis during my Masters in Electrical Engineering in SJSU. The main reason I was interested in this topic had an environmental concern and that was the amount of power that could be saved by going in for asynchronous design.

"Sobre este título" puede pertenecer a otra edición de este libro.

Editorial
LAP LAMBERT Academic Publishing
Año de publicación
2011
Idioma
Inglés
ISBN 10 
3846518441
ISBN 13 
9783846518441
Encuadernación
Tapa blanda
Número de páginas
92
Contacto del fabricante
no disponible
Persona responsable
no disponible