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Cost-effective Methods for High-speed Nanometer CMOS VLSI Design: Interconnect and Circuits - Tapa blanda
Sinopsis
The semiconductor industry has been following Moore?s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.
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Reseña del editor
The semiconductor industry has been following Moore's law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.
Biografía del autor
Charbel Akl received a M.S. in Computer Engineering from University of Balamand, Lebanon, in 2004, and a PhD in Computer Engineering from University of Louisiana at Lafayette in 2008. After graduation, he joined Intel Corporation where he is currently working on the design and implementation of low power microprocessors.
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Cost-effective Methods for High-speed Nanometer CMOS VLSI Design
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LAP LAMBERT Academic Publishing Mai 2010, 2010
ISBN 10: 3838307321
ISBN 13: 9783838307329
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Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The semiconductor industry has been following Moore s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs. 132 pp. Englisch. Nº de ref. del artículo: 9783838307329
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Cost-effective Methods for High-speed Nanometer CMOS VLSI Design
Publicado por
LAP LAMBERT Academic Publishing, 2010
ISBN 10: 3838307321
ISBN 13: 9783838307329
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Tapa blanda
Librería: moluna, Greven, Alemania
Calificación del vendedor: 4 de 5 estrellas
Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Akl CharbelCharbel Akl received a M.S. in Computer Engineering from University of Balamand, Lebanon, in 2004, and a PhD in Computer Engineering from University of Louisiana at Lafayette in 2008. After graduation, he joined Intel . Nº de ref. del artículo: 5411448
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Cost-effective Methods for High-speed Nanometer CMOS VLSI Design
Publicado por
LAP LAMBERT Academic Publishing Mai 2010, 2010
ISBN 10: 3838307321
ISBN 13: 9783838307329
Nuevo
Taschenbuch
Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. Neuware -The semiconductor industry has been following Moore¿s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.Books on Demand GmbH, Überseering 33, 22297 Hamburg 132 pp. Englisch. Nº de ref. del artículo: 9783838307329
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Cost-effective Methods for High-speed Nanometer CMOS VLSI Design : Interconnect and Circuits
Publicado por
LAP LAMBERT Academic Publishing, 2009
ISBN 10: 3838307321
ISBN 13: 9783838307329
Nuevo
Taschenbuch
Librería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The semiconductor industry has been following Moore s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs. Nº de ref. del artículo: 9783838307329
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Cost-effective Methods for High-speed Nanometer CMOS VLSI Design: Interconnect and Circuits
Publicado por
LAP Lambert Academic Publishing, 2009
ISBN 10: 3838307321
ISBN 13: 9783838307329
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Paperback. Condición: Like New. Like New. book. Nº de ref. del artículo: ERICA79038383073216
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