Cost-effective Methods for High-speed Nanometer CMOS VLSI Design: Interconnect and Circuits - Tapa blanda

Akl, Charbel

 
9783838307329: Cost-effective Methods for High-speed Nanometer CMOS VLSI Design: Interconnect and Circuits
Tapa blanda
ISBN 10: 3838307321 ISBN 13: 9783838307329
Editorial: LAP Lambert Academic Publishing, 2009

Sinopsis

The semiconductor industry has been following Moore?s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.

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Reseña del editor

The semiconductor industry has been following Moore's law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.

Biografía del autor

Charbel Akl received a M.S. in Computer Engineering from University of Balamand, Lebanon, in 2004, and a PhD in Computer Engineering from University of Louisiana at Lafayette in 2008. After graduation, he joined Intel Corporation where he is currently working on the design and implementation of low power microprocessors.

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Editorial
LAP Lambert Academic Publishing
Año de publicación
2009
Idioma
Inglés
ISBN 10 
3838307321
ISBN 13 
9783838307329
Encuadernación
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Número de páginas
132
Contacto del fabricante
no disponible
Persona responsable
no disponible

Otras ediciones populares con el mismo título

9786208480622: Cost-effective Methods for High-speed Nanometer CMOS VLSI Design: Interconnect and Circuits. 2nd Edition

Edición Destacada

ISBN 10:  6208480620 ISBN 13:  9786208480622
Editorial: LAP LAMBERT Academic Publishing, 2025
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