Hardware Implementation of AES Encryption and Decryption - Tapa blanda

Abd El Ghany, Mohamed; Al-Maraghi, Mazen

 
9783659928833: Hardware Implementation of AES Encryption and Decryption
Tapa blanda
ISBN 10: 3659928836 ISBN 13: 9783659928833
Editorial: LAP LAMBERT Academic Publishing, 2016

Sinopsis

Nowadays cryptography has a main role in embedded systems design. As the number of devices and applications which send and receive data are increasing rapidly, the data transfer rates are becoming higher. In many applications, this data requires a secured connection which is usually achieved by cryptography. Advanced Encryption Standard (AES) is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. This work presents the AES algorithm and its FPGA implementation. Implementation of the synthesizable and simulation of the VHDL code is carried out on Xilinx - Project Navigator, ISE 13.2i suite. All the transformations of both Encryption and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. This work proposes two new architectures for software and hardware implementations. For the software, a new JAVA application is implemented to provide the user with maximum ease and efficiency in dealing with AES and hardware integration for the AES encryption and decryption algorithm.

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Reseña del editor

Nowadays cryptography has a main role in embedded systems design. As the number of devices and applications which send and receive data are increasing rapidly, the data transfer rates are becoming higher. In many applications, this data requires a secured connection which is usually achieved by cryptography. Advanced Encryption Standard (AES) is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. This work presents the AES algorithm and its FPGA implementation. Implementation of the synthesizable and simulation of the VHDL code is carried out on Xilinx - Project Navigator, ISE 13.2i suite. All the transformations of both Encryption and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. This work proposes two new architectures for software and hardware implementations. For the software, a new JAVA application is implemented to provide the user with maximum ease and efficiency in dealing with AES and hardware integration for the AES encryption and decryption algorithm.

Biografía del autor

Abd El Ghany received the Ph.D degree as a joint degree between German University in Cairo and The Ohio State University in 2010. He was a senior engineer in National Space Agency of Ukraine, EGYPTSAT-1. He was awarded the AvH Postdoctoral Fellowship, Germany. He is an Ass. Prof. In GUC. He is the author of 35 papers, 2 books and 2 book chapters.

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Editorial
LAP LAMBERT Academic Publishing
Año de publicación
2016
Idioma
Inglés
ISBN 10 
3659928836
ISBN 13 
9783659928833
Encuadernación
Tapa blanda
Número de páginas
88
Contacto del fabricante
no disponible
Persona responsable
no disponible