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Sinopsis
This study is based on design and implementation of a 16 bit Arithmetic module, which uses Vedic Mathematics algorithms.The Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E tools. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. Another Model of Vedic Multiplier is proposed by using compressor adder for 8 bit and 16 bit Multiplication that has improved the performance of Multiplier.
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Reseña del editor
This study is based on design and implementation of a 16 bit Arithmetic module, which uses Vedic Mathematics algorithms.The Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E tools. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. Another Model of Vedic Multiplier is proposed by using compressor adder for 8 bit and 16 bit Multiplication that has improved the performance of Multiplier.
Biografía del autor
Dr K.L.Baishnab obtained his BE from (Regional Enginnering College Silchar) (presently National Institute of Technology Silchar INDIA) in the year 1995. M.Tech from Indian Institute of Technology kharagpur (INDIA) in the year 2004. PhD from NIT Silchar 2013.He is currently working as a Asst professor in ECE dept NIT Silchar (INDIA).
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- EditorialLAP LAMBERT Academic Publishing
- Año de publicación2014
- ISBN 10 3659613924
- ISBN 13 9783659613920
- EncuadernaciónTapa blanda
- IdiomaInglés
- Número de páginas92
- Contacto del fabricanteno disponible
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Study and Analysis of Vedic Multipler and 16 Bit Arithmatic Unit
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LAP LAMBERT Academic Publishing Okt 2014, 2014
ISBN 10: 3659613924
ISBN 13: 9783659613920
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Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This study is based on design and implementation of a 16 bit Arithmetic module, which uses Vedic Mathematics algorithms.The Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E tools. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. Another Model of Vedic Multiplier is proposed by using compressor adder for 8 bit and 16 bit Multiplication that has improved the performance of Multiplier. 92 pp. Englisch. Nº de ref. del artículo: 9783659613920
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Study and Analysis of Vedic Multipler and 16 Bit Arithmatic Unit
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LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659613924
ISBN 13: 9783659613920
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Librería: moluna, Greven, Alemania
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Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Baishnab Krishna LalDr K.L.Baishnab obtained his BE from (Regional Enginnering College Silchar) (presently National Institute of Technology Silchar INDIA) in the year 1995. M.Tech from Indian Institute of Technology kharagpur (INDIA). Nº de ref. del artículo: 5168421
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Study and Analysis of Vedic Multipler and 16 Bit Arithmatic Unit
Publicado por
LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659613924
ISBN 13: 9783659613920
Nuevo
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Librería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This study is based on design and implementation of a 16 bit Arithmetic module, which uses Vedic Mathematics algorithms.The Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E tools. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. Another Model of Vedic Multiplier is proposed by using compressor adder for 8 bit and 16 bit Multiplication that has improved the performance of Multiplier. Nº de ref. del artículo: 9783659613920
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Study and Analysis of Vedic Multipler and 16 Bit Arithmatic Unit
Publicado por
LAP LAMBERT Academic Publishing Okt 2014, 2014
ISBN 10: 3659613924
ISBN 13: 9783659613920
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Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
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Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This study is based on design and implementation of a 16 bit Arithmetic module, which uses Vedic Mathematics algorithms.The Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E tools. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. Another Model of Vedic Multiplier is proposed by using compressor adder for 8 bit and 16 bit Multiplication that has improved the performance of Multiplier.Books on Demand GmbH, Überseering 33, 22297 Hamburg 92 pp. Englisch. Nº de ref. del artículo: 9783659613920
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Study and Analysis of Vedic Multipler and 16 Bit Arithmatic Unit
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LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659613924
ISBN 13: 9783659613920
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