Sinopsis
1. Transistors and Gates.- 1.1. Gates with Bipolar Transistors.- 1.2. Gates with Field Effect Transistors.- 1.3. Electrical Characteristics of Gates.- 2. Combinational Circuits.- 2.1. Boolean Algebra.- 2.2. Graphical Notations.- 2.3. Circuit Simplification.- 2.4. The Decoder or Demultiplexer.- 2.5. The Multiplexer.- 2.6. The Adder.- 2.7. The Adder with Fast Carry Generation.- 2.8. The Multiplier.- 2.9. The Read-Only Memory (ROM).- 2.10. The Combinational PLD.- 2.11. The Programmable Gate Array.- 2.12. Dynamic Behaviour of Combinational Circuits.- 3. Latches and Registers.- 3.1. The SR-Latch.- 3.2. The D-Latch.- 3.3. The D-Register.- 3.4. The JK Register.- 4. Synchronous, Sequential Circuits.- 4.1. The State Machine.- 4.2. The Shift Register.- 4.3. The Synchronous Binary Counter.- 4.4. A Design Methodology for State Machines.- 4.5. The PLD and the FPGA with Registers.- 4.6. Timing and Practical Considerations.- 5. Bus Systems.- 5.1. The Concept of a Bus.- 5.2. The Open-Collector Circuit.- 5.3. The Tri-state Gate.- 6. Memories.- 6.1. Static Memories.- 6.2. Dynamic Memories.- 6.3. Dual-Port Memories.- 7. Formal Description of Synchronous Circuits.- 7.1. Motivation.- 7.2. Lola: A Formal Notation for Synchronous Circuits.- 7.3. Examples of Textual Circuit Descriptions.- 8. Design of an Elementary Computer.- 8.1. The Design of von Neumann.- 8.2. Choice of a Specific Architecture.- 8.3. The Arithmetic-Logic Unit (ALU).- 8.4. The Control Unit.- 8.5. Phase Control and Instruction Decoding.- 8.6. An Implementation Using Standard Parts.- 8.7. Interrupts.- 9. Multiplication and Division.- 9.1. Multiplication of Natural Numbers.- 9.2. Division of Natural Numbers.- 9.3. Extending the ALU by a Multiplier-Quotient Register.- 10. Design of a Computer Based on a Microprocessor.- 11. Interfaces Between Asynchronous Units.- 11.1. The Handshake Protocol.- 11.2. Processor-Bus Interfaces.- 11.3. Adding an I/O Interface to the Hercules Computer.- 12. Serial Data Transmission.- 12.1. Introduction.- 12.2. Synchronous Transmission.- 12.3. Asynchronous Transmission.- 12.4. A Buffered Transmitter and Receiver.- Appendix 1: Implementations Based on the Programmable Gate Array AT6002.- 1. The Laboratory.- 2. The Structure of the Gate Array.- 3. The FPGA Extension Board.- 4. A Set of Design Examples.- Appendix 2: Syntax of Lola.- Selected Design Exercises.
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