Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs (Embedded Systems) - Tapa blanda

Acerca del autor

Sven Goossens received his M.Sc. in Embedded Systems from the Eindhoven University of Technology in 2010. He worked as a researcher in the Electrical Engineering of the same university until 2011, and then started as a Ph.D. student, graduating in 2015. He is currently employed as a Hardware Architect at Intrinsic-ID. His research interests include mixed time-criticality systems, composability and SDRAM controllers.

Benny Akesson received his M.Sc. degree at Lund Institute of Technology, Sweden in 2005 and a Ph.D. from Eindhoven University of Technology, the Netherlands in 2010. Since then, he has been employed as a Researcher at Eindhoven University of Technology, Czech Technical University in Prague, and CISTER/INESC TEC Research Unit in Porto. Currently, he is working as a Research Fellow at TNO-ESI. His research interests include memory controller architectures, real-time scheduling, performance modeling, and performance virtualization. He has published more than 50 peer-reviewed conference papers and journal articles, as well as two books about memory controllers for real-time embedded systems.

Kees Goossens received his Ph.D. in Computer Science from the University of Edinburgh in 1993. He worked for Philips/NXP Research from 1995 to 2010 on networks-onchips for consumer electronics, where real-time performance, predictability, and costs are major constraints. He was part-time professor at Delft University from 2007 to 2010, and is now full professor at the Eindhoven University of Technology, where his research focuses on composable (virtualized), predictable (real-time), low-power embedded systems, supporting multiple models of computation. He published 4 books, 100+ papers, and 24 patents.

De la contraportada

This book discusses thedesign and performance analysis of SDRAM controllers that cater to bothreal-time and best-effort applications, i.e. mixed-time-criticality memorycontrollers. The authors describe the state of the art, and then focus on anarchitecture template for reconfigurable memory controllers that addresseseffectively the quickly evolving set of SDRAM standards, in terms of worst-casetiming and power analysis, as well as implementation. A prototypeimplementation of the controller in SystemC and synthesizable VHDL for an FPGAdevelopment board are used as a proof of concept of the architecture template.