Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs - Tapa blanda

Noia, Brandon

9783319345345: Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

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ISBN 10: 3319345346 ISBN 13: 9783319345345

Editorial: Springer, 2016

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This volume encompasses the latest, innovative methods of testing three-dimensional integrated circuits, incorporating pre-bond and post-bond tests as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.

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Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.

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This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs;
Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations;
Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.

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Editorial: Springer
A�o de publicaci�n: 2016
Idioma: Ingl�s
ISBN 10: 3319345346
ISBN 13: 9783319345345
Encuadernaci�n: Tapa blanda
N�mero de p�ginas: 264
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9783319023779: Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

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ISBN 10: 3319023772 ISBN 13: 9783319023779
Editorial: Springer, 2013
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Brandon Noia|Krishnendu Chakrabarty

Publicado por Springer International Publishing, 2016

ISBN 10: 3319345346 ISBN 13: 9783319345345

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Condici�n: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICsIncludes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule opti. N� de ref. del art�culo: 458602076

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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Krishnendu Chakrabarty

Publicado por Springer International Publishing Aug 2016, 2016

ISBN 10: 3319345346 ISBN 13: 9783319345345

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Taschenbuch. Condici�n: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. 264 pp. Englisch. N� de ref. del art�culo: 9783319345345

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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Krishnendu Chakrabarty

Publicado por Springer International Publishing, 2016

ISBN 10: 3319345346 ISBN 13: 9783319345345

Nuevo Taschenbuch

Librería: AHA-BUCH GmbH, Einbeck, Alemania

Calificaci�n del vendedor: 5 de 5 estrellas

Taschenbuch. Condici�n: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. N� de ref. del art�culo: 9783319345345

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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Krishnendu Chakrabarty

Publicado por Springer International Publishing, Springer International Publishing Aug 2016, 2016

ISBN 10: 3319345346 ISBN 13: 9783319345345

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Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania

Calificaci�n del vendedor: 5 de 5 estrellas

Taschenbuch. Condici�n: Neu. Neuware -This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 264 pp. Englisch. N� de ref. del art�culo: 9783319345345

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