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Sinopsis
This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors' combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.
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De la contraportada
This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.
· Describes the state-of-the-art on pipeline-level parallelism and multimedia MPSoCs;
· Includes analytical models and estimation methods for performance estimation of pipelined MPSoCs;
· Covers several design space exploration techniques for pipelined MPSoCs;
· Introduces an adaptive pipelined MPSoC with run-time processor and power managers;
· Introduces Multi-mode pipelined MPSoCs for multiple applications.
"Sobre este título" puede pertenecer a otra edición de este libro.
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Pipelined Multiprocessor System-on-Chip for Multimedia
Librería: Goodwill of Silicon Valley, SAN JOSE, CA, Estados Unidos de America
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Condición: very_good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in very good condition! The cover and any other included accessories are also in very good condition showing some minor use. The spine is straight, there are no rips tears or creases on the cover or the pages. Nº de ref. del artículo: GWSVV.331901112X.VG
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Pipelined Multiprocessor System-on-Chip for Multimedia
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Springer International Publishing, 2013
ISBN 10: 331901112X
ISBN 13: 9783319011127
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Librería: Buchpark, Trebbin, Alemania
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PIPELINED MULTIPROCESSOR SYSTEM ON CHIP FOR MULTIMEDIA (HB 2014)
Librería: Romtrade Corp., STERLING HEIGHTS, MI, Estados Unidos de America
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PIPELINED MULTIPROCESSOR SYSTEM ON CHIP FOR MULTIMEDIA (HB 2014)
Librería: SMASS Sellers, IRVING, TX, Estados Unidos de America
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Condición: New. Brand New Original US Edition. Customer service! Satisfaction Guaranteed. Nº de ref. del artículo: ASNT3-291157
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Pipelined Multiprocessor System-on-Chip for Multimedia
Publicado por
Springer International Publishing, 2013
ISBN 10: 331901112X
ISBN 13: 9783319011127
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Librería: moluna, Greven, Alemania
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Gebunden. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Describes the state-of-the-art on pipeline-level parallelism and multimedia MPSoCsIncludes analytical models and estimation methods for performance estimation of pipelined MPSoCsCovers several design space exploration techniques for pipelin. Nº de ref. del artículo: 4496053
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Pipelined Multiprocessor System-on-Chip for Multimedia
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Springer International Publishing Dez 2013, 2013
ISBN 10: 331901112X
ISBN 13: 9783319011127
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Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
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Buch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors' combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes. 180 pp. Englisch. Nº de ref. del artículo: 9783319011127
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Pipelined Multiprocessor System-on-Chip for Multimedia
Publicado por
Springer International Publishing, 2013
ISBN 10: 331901112X
ISBN 13: 9783319011127
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Librería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors' combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes. Nº de ref. del artículo: 9783319011127
Cantidad disponible: 1 disponibles
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Pipelined Multiprocessor System-on-Chip for Multimedia
Librería: Ria Christie Collections, Uxbridge, Reino Unido
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Condición: New. In. Nº de ref. del artículo: ria9783319011127_new
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Pipelined Multiprocessor System-On-Chip for Multimedia
Librería: Books Puddle, New York, NY, Estados Unidos de America
Calificación del vendedor: 4 de 5 estrellas
Condición: New. pp. 180. Nº de ref. del artículo: 2697857069
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Pipelined Multiprocessor System-On-Chip for Multimedia
Librería: Majestic Books, Hounslow, Reino Unido
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Condición: New. pp. 180 40 Illus. (32 Col.). Nº de ref. del artículo: 94540274
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