A Pipelined Multi-Core Machine with Operating System Support: Hardware Implementation and Correctness Proof: 9999 (Theoretical Computer Science and General Issues) - Tapa blanda

Lutsyk, Petro; Oberhauser, Jonas; Paul, Wolfgang J.

 
9783030432423: A Pipelined Multi-Core Machine with Operating System Support: Hardware Implementation and Correctness Proof: 9999 (Theoretical Computer Science and General Issues)
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ISBN 10: 3030432424 ISBN 13: 9783030432423
Editorial: Springer, 2020

Sinopsis

This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.

It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

• MIPS instruction set architecture (ISA) for application and for system programming

• cache coherent memory system

• store buffers in front of the data caches

• interrupts and exceptions

• memory management units (MMUs)

• pipelined processors: the classical five-stage pipeline is extended by two pipeline

stages for address translation

• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)

• I/O-interrupt controller and a disk

 

"Sinopsis" puede pertenecer a otra edición de este libro.

Acerca del autor

Charlotte y Peter Fiell son dos autoridades en historia, teoría y crítica del diseño y han escrito más de sesenta libros sobre la materia, muchos de los cuales se han convertido en éxitos de ventas. También han impartido conferencias y cursos como profesores invitados, han comisariado exposiciones y asesorado a fabricantes, museos, salas de subastas y grandes coleccionistas privados de todo el mundo. Los Fiell han escrito numerosos libros para TASCHEN, entre los que se incluyen 1000 Chairs, Diseño del siglo XX, El diseño industrial de la A a la Z, Scandinavian Design y Diseño del siglo XXI.

De la contraportada

<div><p>This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.</p><p>It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:</p><p>• MIPS instruction set architecture (ISA) for application and for system programming</p><p>• cache coherent memory system</p><p>• store buffers in front of the data caches</p><p>• interrupts and exceptions</p><p>• memory management units (MMUs)</p><p>• pipelined processors: the classical five-stage pipeline is extended by two pipeline</p><p>stages for address translation</p><p>• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)</p><p><p>• I/O-interrupt controller and a disk</p></p><br><p><br></p><p>&nbsp;</p></div>

"Sobre este título" puede pertenecer a otra edición de este libro.

Editorial
Springer
Año de publicación
2020
Idioma
Inglés
ISBN 10 
3030432424
ISBN 13 
9783030432423
Encuadernación
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Número de edición
1
Número de páginas
644
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Otras ediciones populares con el mismo título

9783030432447: A Pipelined Multi-Core Machine with Operating System Support: Hardware Implementation and Correctness Proof

Edición Destacada

ISBN 10:  3030432440 ISBN 13:  9783030432447
Editorial: Springer, 2020
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