Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures - Tapa dura

Acerca del autor

Kanchan Manna is currently an assistant professor in Department of Computer Science and Engineering, Indian Institute of Technology (IIT) Patna, India. Prior to this, he has worked as a post-doctoral scientist in the Department of Electrical and Computer Engineering (ECE) at George Washington University (GWU), Washington-DC, USA. He earned the MS degree in information technology from Indian Institute of Technology (IIT) Kharagpur, India and the PhD degree in computer science engineering from IIT Kharagpur. His current research interests include Network-on-Chip (NoC) based multicore architecture design, performance and cost evaluation, application mapping in 2D and 3D environments, including thermal-safety, reliability, fault-tolerant and testing.

De la contraportada

This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.  It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications.  

• Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems;
• Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems;
• Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.