Analysis and Design of CMOS Clocking Circuits For Low Phase Noise (Materials, Circuits and Devices) - Tapa dura

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Woorham Bae received the B.S. and Ph.D. degrees in Electrical and Computer Engineering from Seoul National University, Seoul, Korea, in 2010 and 2016, respectively. In 2016, he was with the Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea. From 2017 to 2019, he was with the University of California, Berkeley, CA, as a Postdoctoral Researcher. He is currently a Senior SerDes Engineer with Ayar Labs, Santa Clara, CA. His current research interests include integrated circuits for silicon photonics, high-speed I/O circuits and architectures, nonvolatile memory systems, and agile hardware design methodology. Dr. Bae received the IEEE Circuits and Systems Society Outstanding Young Author Award in 2018, the Distinguished Ph.D. Dissertation Award from the Department of Electrical and Computer Engineering, Seoul National University in 2016, the IEEE Circuits and Systems Society Pre-Doctoral Scholarship in 2016, and the IEEE Solid-State Circuits Society STG Award in 2015.

Deog-Kyoon Jeong received the B.S. and M.S. degrees in Electronics Engineering from Seoul National University, Seoul, South Korea, in 1981 and 1984, respectively, and the Ph.D. degree in Electrical Engineering and Computer Sciences from the University of California at Berkeley, Berkeley, CA, USA, in 1989. From 1989 to 1991, he was a member of the Technical Staff with Texas Instruments, Dallas, TX, USA. He worked on the modeling and design of BiCMOS gates and the single-chip implementation of the SPARC architecture. Then, he joined the faculty of the Department of Electronics Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea, where he is currently an Endowed-Chair Professor. He was one of cofounders of Silicon Image, Sunnyvale, CA, now Lattice Semiconductor, which specialized in digital interface circuits for video displays such as DVI and HDMI. His main research interests include the design of high-speed I/O circuits, phase-locked loops, and memory system architecture. Dr. Jeong was a recipient of the ISSCC Takuo Sugano Award in 2005 for Outstanding Far-East Paper. He is a Fellow of the IEEE.