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Sinopsis
Real Chip Design and Verification Using Verilog and VHDL addresses the practical and real aspects of logic design, processes, and verification. It incorporates a collection of FPGA and ASIC design practices, and uses Verilog and VHDL as a tool for expression of the desired architectures. This book is not intended to teach either HDL, as there are several books specifically geared toward teaching the languages. However, it provides various architectural design primitives, applications, and verification techniques, along with design methodologies and common practices.
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Real Chip Design and Verification Using Verilog and VHDL addresses the practical and real aspects of logic design, processes, and verification. It incorporates a collection of FPGA and ASIC design practices, and uses Verilog and VHDL as a tool for expression of the desired architectures. This book is not intended to teach either HDL, as there are several books specifically geared toward teaching the languages. However, it provides various architectural design primitives, applications, and verification techniques, along with design methodologies and common practices.
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Real Chip Design and Verification Using Verilog and VHDL
Publicado por
Createspace Independent Publishing Platform, 2002
ISBN 10: 1539769712
ISBN 13: 9781539769712
Nuevo
Paperback / softback
Librería: THE SAINT BOOKSTORE, Southport, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Paperback / softback. Condición: New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 980. Nº de ref. del artículo: C9781539769712
Cantidad disponible: Más de 20 disponibles
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Real Chip Design and Verification Using Verilog and VHDL (Paperback)
Publicado por
Createspace Independent Publishing Platform, 2002
ISBN 10: 1539769712
ISBN 13: 9781539769712
Nuevo
Paperback
Librería: CitiRetail, Stevenage, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Paperback. Condición: new. Paperback. Real Chip Design and Verification Using Verilog and VHDL addresses the practical and real aspects of logic design, processes, and verification. It incorporates a collection of FPGA and ASIC design practices, and uses Verilog and VHDL as a tool for expression of the desired architectures. This book is not intended to teach either HDL, as there are several books specifically geared toward teaching the languages. However, it provides various architectural design primitives, applications, and verification techniques, along with design methodologies and common practices. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability. Nº de ref. del artículo: 9781539769712
Cantidad disponible: 1 disponibles