Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx.
Sridhar Gangadharan is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.
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Descripción Kartoniert / Broschiert. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides a hands-on guide to create constraints for synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints Explains fundamental concepts around SDC constraints and its applica. Nº de ref. del artículo: 33841351